arm: Add support for tracking TCs in ISA devices

ISA devices typically need to keep track of the thread context they
are associated with. Among other things, this is required for
interrupt delivery. Add a BaseISADevice:setThreadContext() method to
wire such models to the right thread context.

Change-Id: Iad354d176c0c4c4e34c6ab8b5acaee0b69da0406
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12399
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

src/arch/arm/isa.cc

@@ -329,6 +329,14 @@ ISA::clear64(const ArmISAParams *p)
         encodePhysAddrRange64(physAddrRange64));
 }
 
+void
+ISA::startup(ThreadContext *tc)
+{
+    pmu->setThreadContext(tc);
+
+}
+
+
 MiscReg
 ISA::readMiscRegNoEffect(int misc_reg) const
 {
@@ -1946,6 +1954,8 @@ ISA::getGenericTimer(ThreadContext *tc)
     }
 
     timer.reset(new GenericTimerISA(*generic_timer, tc->contextId()));
+    timer->setThreadContext(tc);
+
     return *timer.get();
 }
 

src/arch/arm/isa.hh

@@ -659,7 +659,7 @@ namespace ArmISA
             UNSERIALIZE_SCALAR(physAddrRange64);
         }
 
-        void startup(ThreadContext *tc) {}
+        void startup(ThreadContext *tc);
 
         Enums::DecoderFlavour decoderFlavour() const { return _decoderFlavour; }
 

src/arch/arm/isa_device.hh

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014 ARM Limited
+ * Copyright (c) 2014, 2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -43,6 +43,8 @@
 #include "arch/arm/registers.hh"
 #include "base/compiler.hh"
 
+class ThreadContext;
+
 namespace ArmISA
 {
 
@@ -62,6 +64,7 @@ class BaseISADevice
     virtual ~BaseISADevice() {}
 
     virtual void setISA(ISA *isa);
+    virtual void setThreadContext(ThreadContext *tc) {}
 
     /**
      * Write to a system register belonging to this device.