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dev, arm: Add misc reg tracing to the generic timer

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Change-Id: Ice9376b8eb42423679b0191910e8c980f8017f88
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12398
This commit is contained in:
Andreas Sandberg
2018-03-22 17:58:59 +00:00
committed by Giacomo Travaglini
parent a3e0eb0b24
commit 476fd104a8
2 changed files with 18 additions and 8 deletions
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16
src/dev/arm/generic_timer.cc
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2013, 2015, 2017 ARM Limited
* Copyright (c) 2013, 2015, 2017-2018 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -521,6 +521,20 @@ GenericTimer::readMiscReg(int reg, unsigned cpu)
}
void
GenericTimerISA::setMiscReg(int reg, MiscReg val)
{
DPRINTF(Timer, "Setting %s := 0x%x\n", miscRegName[reg], val);
parent.setMiscReg(reg, cpu, val);
}
MiscReg
GenericTimerISA::readMiscReg(int reg)
{
MiscReg value = parent.readMiscReg(reg, cpu);
DPRINTF(Timer, "Reading %s as 0x%x\n", miscRegName[reg], value);
return value;
}
GenericTimerMem::GenericTimerMem(GenericTimerMemParams *p)
: PioDevice(p),

10
src/dev/arm/generic_timer.hh
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2013, 2015, 2017 ARM Limited
* Copyright (c) 2013, 2015, 2017-2018 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -318,12 +318,8 @@ class GenericTimerISA : public ArmISA::BaseISADevice
GenericTimerISA(GenericTimer &_parent, unsigned _cpu)
: parent(_parent), cpu(_cpu) {}
void setMiscReg(int misc_reg, ArmISA::MiscReg val) override {
parent.setMiscReg(misc_reg, cpu, val);
}
ArmISA::MiscReg readMiscReg(int misc_reg) override {
return parent.readMiscReg(misc_reg, cpu);
}
void setMiscReg(int misc_reg, ArmISA::MiscReg val) override;
ArmISA::MiscReg readMiscReg(int misc_reg) override;
protected:
GenericTimer &parent;