fbaf489e62
ISA devices typically need to keep track of the thread context they are associated with. Among other things, this is required for interrupt delivery. Add a BaseISADevice:setThreadContext() method to wire such models to the right thread context. Change-Id: Iad354d176c0c4c4e34c6ab8b5acaee0b69da0406 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12399 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
697 lines
24 KiB
C++
697 lines
24 KiB
C++
/*
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* Copyright (c) 2010, 2012-2018 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2009 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_ARM_ISA_HH__
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#define __ARCH_ARM_ISA_HH__
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#include "arch/arm/isa_device.hh"
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#include "arch/arm/miscregs.hh"
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#include "arch/arm/registers.hh"
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#include "arch/arm/system.hh"
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#include "arch/arm/tlb.hh"
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#include "arch/arm/types.hh"
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#include "arch/generic/traits.hh"
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#include "debug/Checkpoint.hh"
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#include "enums/VecRegRenameMode.hh"
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#include "sim/sim_object.hh"
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#include "enums/DecoderFlavour.hh"
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struct ArmISAParams;
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struct DummyArmISADeviceParams;
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class ThreadContext;
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class Checkpoint;
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class EventManager;
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namespace ArmISA
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{
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class ISA : public SimObject
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{
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protected:
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// Parent system
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ArmSystem *system;
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// Micro Architecture
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const Enums::DecoderFlavour _decoderFlavour;
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const Enums::VecRegRenameMode _vecRegRenameMode;
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/** Dummy device for to handle non-existing ISA devices */
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DummyISADevice dummyDevice;
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// PMU belonging to this ISA
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BaseISADevice *pmu;
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// Generic timer interface belonging to this ISA
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std::unique_ptr<BaseISADevice> timer;
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// Cached copies of system-level properties
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bool highestELIs64;
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bool haveSecurity;
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bool haveLPAE;
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bool haveVirtualization;
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bool haveLargeAsid64;
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uint8_t physAddrRange64;
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/**
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* If true, accesses to IMPLEMENTATION DEFINED registers are treated
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* as NOP hence not causing UNDEFINED INSTRUCTION.
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*/
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bool impdefAsNop;
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/** MiscReg metadata **/
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struct MiscRegLUTEntry {
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uint32_t lower; // Lower half mapped to this register
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uint32_t upper; // Upper half mapped to this register
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uint64_t _reset; // value taken on reset (i.e. initialization)
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uint64_t _res0; // reserved
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uint64_t _res1; // reserved
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uint64_t _raz; // read as zero (fixed at 0)
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uint64_t _rao; // read as one (fixed at 1)
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public:
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MiscRegLUTEntry() :
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lower(0), upper(0),
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_reset(0), _res0(0), _res1(0), _raz(0), _rao(0) {}
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uint64_t reset() const { return _reset; }
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uint64_t res0() const { return _res0; }
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uint64_t res1() const { return _res1; }
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uint64_t raz() const { return _raz; }
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uint64_t rao() const { return _rao; }
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// raz/rao implies writes ignored
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uint64_t wi() const { return _raz | _rao; }
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};
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/** Metadata table accessible via the value of the register */
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static std::vector<struct MiscRegLUTEntry> lookUpMiscReg;
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class MiscRegLUTEntryInitializer {
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struct MiscRegLUTEntry &entry;
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std::bitset<NUM_MISCREG_INFOS> &info;
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typedef const MiscRegLUTEntryInitializer& chain;
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public:
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chain mapsTo(uint32_t l, uint32_t u = 0) const {
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entry.lower = l;
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entry.upper = u;
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return *this;
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}
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chain res0(uint64_t mask) const {
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entry._res0 = mask;
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return *this;
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}
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chain res1(uint64_t mask) const {
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entry._res1 = mask;
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return *this;
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}
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chain raz(uint64_t mask) const {
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entry._raz = mask;
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return *this;
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}
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chain rao(uint64_t mask) const {
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entry._rao = mask;
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return *this;
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}
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chain implemented(bool v = true) const {
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info[MISCREG_IMPLEMENTED] = v;
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return *this;
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}
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chain unimplemented() const {
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return implemented(false);
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}
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chain unverifiable(bool v = true) const {
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info[MISCREG_UNVERIFIABLE] = v;
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return *this;
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}
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chain warnNotFail(bool v = true) const {
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info[MISCREG_WARN_NOT_FAIL] = v;
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return *this;
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}
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chain mutex(bool v = true) const {
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info[MISCREG_MUTEX] = v;
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return *this;
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}
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chain banked(bool v = true) const {
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info[MISCREG_BANKED] = v;
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return *this;
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}
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chain bankedChild(bool v = true) const {
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info[MISCREG_BANKED_CHILD] = v;
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return *this;
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}
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chain userNonSecureRead(bool v = true) const {
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info[MISCREG_USR_NS_RD] = v;
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return *this;
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}
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chain userNonSecureWrite(bool v = true) const {
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info[MISCREG_USR_NS_WR] = v;
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return *this;
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}
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chain userSecureRead(bool v = true) const {
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info[MISCREG_USR_S_RD] = v;
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return *this;
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}
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chain userSecureWrite(bool v = true) const {
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info[MISCREG_USR_S_WR] = v;
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return *this;
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}
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chain user(bool v = true) const {
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userNonSecureRead(v);
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userNonSecureWrite(v);
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userSecureRead(v);
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userSecureWrite(v);
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return *this;
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}
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chain privNonSecureRead(bool v = true) const {
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info[MISCREG_PRI_NS_RD] = v;
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return *this;
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}
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chain privNonSecureWrite(bool v = true) const {
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info[MISCREG_PRI_NS_WR] = v;
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return *this;
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}
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chain privNonSecure(bool v = true) const {
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privNonSecureRead(v);
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privNonSecureWrite(v);
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return *this;
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}
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chain privSecureRead(bool v = true) const {
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info[MISCREG_PRI_S_RD] = v;
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return *this;
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}
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chain privSecureWrite(bool v = true) const {
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info[MISCREG_PRI_S_WR] = v;
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return *this;
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}
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chain privSecure(bool v = true) const {
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privSecureRead(v);
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privSecureWrite(v);
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return *this;
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}
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chain priv(bool v = true) const {
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privSecure(v);
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privNonSecure(v);
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return *this;
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}
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chain hypRead(bool v = true) const {
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info[MISCREG_HYP_RD] = v;
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return *this;
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}
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chain hypWrite(bool v = true) const {
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info[MISCREG_HYP_WR] = v;
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return *this;
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}
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chain hyp(bool v = true) const {
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hypRead(v);
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hypWrite(v);
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return *this;
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}
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chain monSecureRead(bool v = true) const {
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info[MISCREG_MON_NS0_RD] = v;
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return *this;
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}
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chain monSecureWrite(bool v = true) const {
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info[MISCREG_MON_NS0_WR] = v;
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return *this;
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}
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chain monNonSecureRead(bool v = true) const {
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info[MISCREG_MON_NS1_RD] = v;
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return *this;
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}
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chain monNonSecureWrite(bool v = true) const {
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info[MISCREG_MON_NS1_WR] = v;
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return *this;
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}
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chain mon(bool v = true) const {
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monSecureRead(v);
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monSecureWrite(v);
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monNonSecureRead(v);
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monNonSecureWrite(v);
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return *this;
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}
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chain monSecure(bool v = true) const {
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monSecureRead(v);
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monSecureWrite(v);
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return *this;
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}
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chain monNonSecure(bool v = true) const {
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monNonSecureRead(v);
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monNonSecureWrite(v);
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return *this;
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}
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chain allPrivileges(bool v = true) const {
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userNonSecureRead(v);
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userNonSecureWrite(v);
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userSecureRead(v);
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userSecureWrite(v);
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privNonSecureRead(v);
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privNonSecureWrite(v);
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privSecureRead(v);
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privSecureWrite(v);
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hypRead(v);
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hypWrite(v);
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monSecureRead(v);
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monSecureWrite(v);
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monNonSecureRead(v);
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monNonSecureWrite(v);
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return *this;
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}
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chain nonSecure(bool v = true) const {
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userNonSecureRead(v);
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userNonSecureWrite(v);
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privNonSecureRead(v);
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privNonSecureWrite(v);
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hypRead(v);
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hypWrite(v);
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monNonSecureRead(v);
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monNonSecureWrite(v);
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return *this;
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}
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chain secure(bool v = true) const {
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userSecureRead(v);
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userSecureWrite(v);
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privSecureRead(v);
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privSecureWrite(v);
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monSecureRead(v);
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monSecureWrite(v);
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return *this;
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}
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chain reads(bool v) const {
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userNonSecureRead(v);
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userSecureRead(v);
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privNonSecureRead(v);
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privSecureRead(v);
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hypRead(v);
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monSecureRead(v);
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monNonSecureRead(v);
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return *this;
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}
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chain writes(bool v) const {
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userNonSecureWrite(v);
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userSecureWrite(v);
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privNonSecureWrite(v);
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privSecureWrite(v);
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hypWrite(v);
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monSecureWrite(v);
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monNonSecureWrite(v);
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return *this;
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}
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chain exceptUserMode() const {
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user(0);
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return *this;
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}
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MiscRegLUTEntryInitializer(struct MiscRegLUTEntry &e,
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std::bitset<NUM_MISCREG_INFOS> &i)
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: entry(e),
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info(i)
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{
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// force unimplemented registers to be thusly declared
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implemented(1);
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}
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};
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const MiscRegLUTEntryInitializer InitReg(uint32_t reg) {
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return MiscRegLUTEntryInitializer(lookUpMiscReg[reg],
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miscRegInfo[reg]);
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}
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void initializeMiscRegMetadata();
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MiscReg miscRegs[NumMiscRegs];
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const IntRegIndex *intRegMap;
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void
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updateRegMap(CPSR cpsr)
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{
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if (cpsr.width == 0) {
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intRegMap = IntReg64Map;
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} else {
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switch (cpsr.mode) {
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case MODE_USER:
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case MODE_SYSTEM:
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intRegMap = IntRegUsrMap;
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break;
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case MODE_FIQ:
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intRegMap = IntRegFiqMap;
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break;
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case MODE_IRQ:
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intRegMap = IntRegIrqMap;
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break;
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case MODE_SVC:
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intRegMap = IntRegSvcMap;
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break;
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case MODE_MON:
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intRegMap = IntRegMonMap;
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break;
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case MODE_ABORT:
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intRegMap = IntRegAbtMap;
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break;
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case MODE_HYP:
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intRegMap = IntRegHypMap;
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break;
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case MODE_UNDEFINED:
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intRegMap = IntRegUndMap;
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break;
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default:
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panic("Unrecognized mode setting in CPSR.\n");
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}
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}
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}
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BaseISADevice &getGenericTimer(ThreadContext *tc);
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private:
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inline void assert32(ThreadContext *tc) {
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CPSR cpsr M5_VAR_USED = readMiscReg(MISCREG_CPSR, tc);
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assert(cpsr.width);
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}
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inline void assert64(ThreadContext *tc) {
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CPSR cpsr M5_VAR_USED = readMiscReg(MISCREG_CPSR, tc);
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assert(!cpsr.width);
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}
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public:
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void clear();
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void clear64(const ArmISAParams *p);
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MiscReg readMiscRegNoEffect(int misc_reg) const;
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MiscReg readMiscReg(int misc_reg, ThreadContext *tc);
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void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
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void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
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RegId
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flattenRegId(const RegId& regId) const
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{
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switch (regId.classValue()) {
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case IntRegClass:
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return RegId(IntRegClass, flattenIntIndex(regId.index()));
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case FloatRegClass:
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return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
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case VecRegClass:
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return RegId(VecRegClass, flattenVecIndex(regId.index()));
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case VecElemClass:
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return RegId(VecElemClass, flattenVecElemIndex(regId.index()));
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case CCRegClass:
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return RegId(CCRegClass, flattenCCIndex(regId.index()));
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case MiscRegClass:
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return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
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}
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return RegId();
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}
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int
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flattenIntIndex(int reg) const
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{
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assert(reg >= 0);
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if (reg < NUM_ARCH_INTREGS) {
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return intRegMap[reg];
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} else if (reg < NUM_INTREGS) {
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return reg;
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} else if (reg == INTREG_SPX) {
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CPSR cpsr = miscRegs[MISCREG_CPSR];
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ExceptionLevel el = opModeToEL(
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(OperatingMode) (uint8_t) cpsr.mode);
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if (!cpsr.sp && el != EL0)
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return INTREG_SP0;
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switch (el) {
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case EL3:
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return INTREG_SP3;
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case EL2:
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return INTREG_SP2;
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case EL1:
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return INTREG_SP1;
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case EL0:
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return INTREG_SP0;
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default:
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panic("Invalid exception level");
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break;
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}
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} else {
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return flattenIntRegModeIndex(reg);
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}
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}
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int
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flattenFloatIndex(int reg) const
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{
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assert(reg >= 0);
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return reg;
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}
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int
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flattenVecIndex(int reg) const
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{
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assert(reg >= 0);
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return reg;
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}
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int
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flattenVecElemIndex(int reg) const
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{
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assert(reg >= 0);
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return reg;
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}
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int
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flattenCCIndex(int reg) const
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{
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assert(reg >= 0);
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return reg;
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}
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int
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flattenMiscIndex(int reg) const
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{
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assert(reg >= 0);
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int flat_idx = reg;
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if (reg == MISCREG_SPSR) {
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CPSR cpsr = miscRegs[MISCREG_CPSR];
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switch (cpsr.mode) {
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case MODE_EL0T:
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warn("User mode does not have SPSR\n");
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flat_idx = MISCREG_SPSR;
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break;
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case MODE_EL1T:
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case MODE_EL1H:
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flat_idx = MISCREG_SPSR_EL1;
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break;
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case MODE_EL2T:
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case MODE_EL2H:
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flat_idx = MISCREG_SPSR_EL2;
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break;
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case MODE_EL3T:
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case MODE_EL3H:
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flat_idx = MISCREG_SPSR_EL3;
|
|
break;
|
|
case MODE_USER:
|
|
warn("User mode does not have SPSR\n");
|
|
flat_idx = MISCREG_SPSR;
|
|
break;
|
|
case MODE_FIQ:
|
|
flat_idx = MISCREG_SPSR_FIQ;
|
|
break;
|
|
case MODE_IRQ:
|
|
flat_idx = MISCREG_SPSR_IRQ;
|
|
break;
|
|
case MODE_SVC:
|
|
flat_idx = MISCREG_SPSR_SVC;
|
|
break;
|
|
case MODE_MON:
|
|
flat_idx = MISCREG_SPSR_MON;
|
|
break;
|
|
case MODE_ABORT:
|
|
flat_idx = MISCREG_SPSR_ABT;
|
|
break;
|
|
case MODE_HYP:
|
|
flat_idx = MISCREG_SPSR_HYP;
|
|
break;
|
|
case MODE_UNDEFINED:
|
|
flat_idx = MISCREG_SPSR_UND;
|
|
break;
|
|
default:
|
|
warn("Trying to access SPSR in an invalid mode: %d\n",
|
|
cpsr.mode);
|
|
flat_idx = MISCREG_SPSR;
|
|
break;
|
|
}
|
|
} else if (miscRegInfo[reg][MISCREG_MUTEX]) {
|
|
// Mutually exclusive CP15 register
|
|
switch (reg) {
|
|
case MISCREG_PRRR_MAIR0:
|
|
case MISCREG_PRRR_MAIR0_NS:
|
|
case MISCREG_PRRR_MAIR0_S:
|
|
{
|
|
TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
|
|
// If the muxed reg has been flattened, work out the
|
|
// offset and apply it to the unmuxed reg
|
|
int idxOffset = reg - MISCREG_PRRR_MAIR0;
|
|
if (ttbcr.eae)
|
|
flat_idx = flattenMiscIndex(MISCREG_MAIR0 +
|
|
idxOffset);
|
|
else
|
|
flat_idx = flattenMiscIndex(MISCREG_PRRR +
|
|
idxOffset);
|
|
}
|
|
break;
|
|
case MISCREG_NMRR_MAIR1:
|
|
case MISCREG_NMRR_MAIR1_NS:
|
|
case MISCREG_NMRR_MAIR1_S:
|
|
{
|
|
TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
|
|
// If the muxed reg has been flattened, work out the
|
|
// offset and apply it to the unmuxed reg
|
|
int idxOffset = reg - MISCREG_NMRR_MAIR1;
|
|
if (ttbcr.eae)
|
|
flat_idx = flattenMiscIndex(MISCREG_MAIR1 +
|
|
idxOffset);
|
|
else
|
|
flat_idx = flattenMiscIndex(MISCREG_NMRR +
|
|
idxOffset);
|
|
}
|
|
break;
|
|
case MISCREG_PMXEVTYPER_PMCCFILTR:
|
|
{
|
|
PMSELR pmselr = miscRegs[MISCREG_PMSELR];
|
|
if (pmselr.sel == 31)
|
|
flat_idx = flattenMiscIndex(MISCREG_PMCCFILTR);
|
|
else
|
|
flat_idx = flattenMiscIndex(MISCREG_PMXEVTYPER);
|
|
}
|
|
break;
|
|
default:
|
|
panic("Unrecognized misc. register.\n");
|
|
break;
|
|
}
|
|
} else {
|
|
if (miscRegInfo[reg][MISCREG_BANKED]) {
|
|
bool secureReg = haveSecurity && !highestELIs64 &&
|
|
inSecureState(miscRegs[MISCREG_SCR],
|
|
miscRegs[MISCREG_CPSR]);
|
|
flat_idx += secureReg ? 2 : 1;
|
|
}
|
|
}
|
|
return flat_idx;
|
|
}
|
|
|
|
std::pair<int,int> getMiscIndices(int misc_reg) const
|
|
{
|
|
// Note: indexes of AArch64 registers are left unchanged
|
|
int flat_idx = flattenMiscIndex(misc_reg);
|
|
|
|
if (lookUpMiscReg[flat_idx].lower == 0) {
|
|
return std::make_pair(flat_idx, 0);
|
|
}
|
|
|
|
// do additional S/NS flattenings if mapped to NS while in S
|
|
bool S = haveSecurity && !highestELIs64 &&
|
|
inSecureState(miscRegs[MISCREG_SCR],
|
|
miscRegs[MISCREG_CPSR]);
|
|
int lower = lookUpMiscReg[flat_idx].lower;
|
|
int upper = lookUpMiscReg[flat_idx].upper;
|
|
// upper == 0, which is CPSR, is not MISCREG_BANKED_CHILD (no-op)
|
|
lower += S && miscRegInfo[lower][MISCREG_BANKED_CHILD];
|
|
upper += S && miscRegInfo[upper][MISCREG_BANKED_CHILD];
|
|
return std::make_pair(lower, upper);
|
|
}
|
|
|
|
void serialize(CheckpointOut &cp) const
|
|
{
|
|
DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
|
|
SERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
|
|
|
|
SERIALIZE_SCALAR(highestELIs64);
|
|
SERIALIZE_SCALAR(haveSecurity);
|
|
SERIALIZE_SCALAR(haveLPAE);
|
|
SERIALIZE_SCALAR(haveVirtualization);
|
|
SERIALIZE_SCALAR(haveLargeAsid64);
|
|
SERIALIZE_SCALAR(physAddrRange64);
|
|
}
|
|
void unserialize(CheckpointIn &cp)
|
|
{
|
|
DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
|
|
UNSERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
|
|
CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
|
|
updateRegMap(tmp_cpsr);
|
|
|
|
UNSERIALIZE_SCALAR(highestELIs64);
|
|
UNSERIALIZE_SCALAR(haveSecurity);
|
|
UNSERIALIZE_SCALAR(haveLPAE);
|
|
UNSERIALIZE_SCALAR(haveVirtualization);
|
|
UNSERIALIZE_SCALAR(haveLargeAsid64);
|
|
UNSERIALIZE_SCALAR(physAddrRange64);
|
|
}
|
|
|
|
void startup(ThreadContext *tc);
|
|
|
|
Enums::DecoderFlavour decoderFlavour() const { return _decoderFlavour; }
|
|
|
|
Enums::VecRegRenameMode
|
|
vecRegRenameMode() const
|
|
{
|
|
return _vecRegRenameMode;
|
|
}
|
|
|
|
/// Explicitly import the otherwise hidden startup
|
|
using SimObject::startup;
|
|
|
|
typedef ArmISAParams Params;
|
|
|
|
const Params *params() const;
|
|
|
|
ISA(Params *p);
|
|
};
|
|
}
|
|
|
|
template<>
|
|
struct initRenameMode<ArmISA::ISA>
|
|
{
|
|
static Enums::VecRegRenameMode mode(const ArmISA::ISA* isa)
|
|
{
|
|
return isa->vecRegRenameMode();
|
|
}
|
|
static bool equals(const ArmISA::ISA* isa1, const ArmISA::ISA* isa2)
|
|
{
|
|
return mode(isa1) == mode(isa2);
|
|
}
|
|
};
|
|
|
|
#endif
|