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2e47c6c5ed37dc1db0ea35f51b2f7d4afc0da45e
gem5/src/arch/riscv
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Gabe Black 5365c18f2e arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy. 
These two functions were performing the same function but had two
different names for historical reasons. This change merges them
together, keeping the getVirtProxy name to be consistent with the
getPhysProxy method used to get a non-translating proxy port.

Change-Id: Idd83c6b899f9343795075b030ccbc723a79e52a4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18581
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-05-30 14:20:03 +00:00
..
bare_metal
arch-riscv: enable rudimentary fs simulation
2018-07-09 11:17:11 +00:00
insts
riscv: fix AMO, LR and SC instructions
2019-02-08 15:27:04 +00:00
isa
arch-riscv,isa: Fix for compressed jump (c_j) imm
2019-05-03 12:53:53 +00:00
linux
arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy.
2019-05-30 14:20:03 +00:00
decoder.cc
riscv,x86: Stop using the arch Nop machine instruction unnecessarily.
2017-12-23 03:36:45 +00:00
decoder.hh
arch: cpu: Make the ExtMachInst type a template argument in InstMap.
2018-03-27 10:57:54 +00:00
faults.cc
riscv: Get rid of some ISA specific register types.
2019-01-31 11:03:21 +00:00
faults.hh
riscv: Get rid of some ISA specific register types.
2019-01-31 11:03:21 +00:00
idle_event.cc
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
2016-11-30 17:10:28 -05:00
idle_event.hh
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
2016-11-30 17:10:28 -05:00
interrupts.cc
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
2016-11-30 17:10:28 -05:00
interrupts.hh
arch-riscv: Initialize interrupt mask
2019-02-06 16:57:48 +00:00
isa_traits.hh
alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT.
2018-01-10 12:19:54 +00:00
isa.cc
arch-riscv: Implement MHARTID CSR
2019-05-04 04:37:19 +00:00
isa.hh
riscv: Get rid of some ISA specific register types.
2019-01-31 11:03:21 +00:00
kernel_stats.hh
stats: Get rid of some kernel stats related cruft.
2017-09-11 04:58:38 +00:00
locked_mem.cc
riscv: fix AMO, LR and SC instructions
2019-02-08 15:27:04 +00:00
locked_mem.hh
riscv: fix AMO, LR and SC instructions
2019-02-08 15:27:04 +00:00
microcode_rom.hh
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
2016-11-30 17:10:28 -05:00
mmapped_ipr.hh
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
2016-11-30 17:10:28 -05:00
pagetable.cc
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
2016-11-30 17:10:28 -05:00
pagetable.hh
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
pra_constants.hh
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
2016-11-30 17:10:28 -05:00
process.cc
arch, sim: Simplify the AuxVector type.
2019-04-28 05:16:01 +00:00
process.hh
arch-riscv: Enable support for riscv 32-bit in SE mode.
2019-02-07 01:48:08 +00:00
pseudo_inst.hh
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
registers.hh
cpu, arch: Replace the CCReg type with RegVal.
2019-02-01 01:22:19 +00:00
remote_gdb.cc
arch: cpu: Rename *FloatRegBits* to *FloatReg*.
2019-01-31 11:02:05 +00:00
remote_gdb.hh
riscv: Get rid of some ISA specific register types.
2019-01-31 11:03:21 +00:00
RiscvInterrupts.py
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
2016-11-30 17:10:28 -05:00
RiscvISA.py
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
2016-11-30 17:10:28 -05:00
RiscvSystem.py
python: Don't assume SimObjects live in the global namespace
2019-02-12 09:43:00 +00:00
RiscvTLB.py
python: Don't assume SimObjects live in the global namespace
2019-02-12 09:43:00 +00:00
SConscript
arch-riscv: enable rudimentary fs simulation
2018-07-09 11:17:11 +00:00
SConsopts
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
2016-11-30 17:10:28 -05:00
stacktrace.cc
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
2016-11-30 17:10:28 -05:00
stacktrace.hh
arch: Stop using TheISA within the ISAs.
2019-04-30 18:52:13 +00:00
system.cc
arch-riscv: enable rudimentary fs simulation
2018-07-09 11:17:11 +00:00
system.hh
arch-riscv: enable rudimentary fs simulation
2018-07-09 11:17:11 +00:00
tlb.cc
arch-riscv: enable rudimentary fs simulation
2018-07-09 11:17:11 +00:00
tlb.hh
misc: Using smart pointers for memory Requests
2018-06-11 16:55:30 +00:00
types.hh
arch-riscv: Enable support for riscv 32-bit in SE mode.
2019-02-07 01:48:08 +00:00
utility.cc
arch-riscv: enable rudimentary fs simulation
2018-07-09 11:17:11 +00:00
utility.hh
arch-riscv: enable rudimentary fs simulation
2018-07-09 11:17:11 +00:00
vtophys.hh
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
2016-11-30 17:10:28 -05:00