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cpu, arch: Replace the CCReg type with RegVal.

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Most architectures weren't using the CCReg type, and in x86 and arm
it was already a uint64_t.

Change-Id: I0b3d5e690e6b31db6f2627f449c89bde0f6750a6
Reviewed-on: https://gem5-review.googlesource.com/c/14515
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
This commit is contained in:
Gabe Black
2018-11-21 16:20:57 -08:00
parent fbdf0b689e
commit a119a96324
23 changed files with 56 additions and 77 deletions
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3
src/arch/alpha/registers.hh
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@@ -46,9 +46,6 @@ using AlphaISAInst::MaxInstDestRegs;
// Locked read/write flags are can't be detected by the ISA parser
const int MaxMiscDestRegs = AlphaISAInst::MaxMiscDestRegs + 1;
// dummy typedef since we don't have CC regs
typedef uint8_t CCReg;
// Not applicable to Alpha
using VecElem = ::DummyVecElem;
using VecReg = ::DummyVecReg;

3
src/arch/arm/registers.hh
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@@ -77,9 +77,6 @@ using VecPredRegContainer = ::DummyVecPredRegContainer;
constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;
constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;
// condition code register; must be at least 32 bits for FpCondCodes
typedef uint64_t CCReg;
// Constants Related to the number of registers
const int NumIntArchRegs = NUM_ARCH_INTREGS;
// The number of single precision floating point registers

3
src/arch/mips/registers.hh
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@@ -283,9 +283,6 @@ const int NumMiscRegs = MISCREG_NUMREGS;
const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
// dummy typedef since we don't have CC regs
typedef uint8_t CCReg;
// Not applicable to MIPS
using VecElem = ::DummyVecElem;
using VecReg = ::DummyVecReg;

1
src/arch/null/registers.hh
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@@ -47,7 +47,6 @@
namespace NullISA {
typedef uint8_t CCReg;
const RegIndex ZeroReg = 0;
// Not applicable to null

3
src/arch/power/registers.hh
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@@ -46,9 +46,6 @@ using PowerISAInst::MaxInstDestRegs;
// be detected by it. Manually add it here.
const int MaxMiscDestRegs = PowerISAInst::MaxMiscDestRegs + 1;
// dummy typedef since we don't have CC regs
typedef uint8_t CCReg;
// Not applicable to Power
using VecElem = ::DummyVecElem;
using VecReg = ::DummyVecReg;

2
src/arch/riscv/registers.hh
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@@ -64,8 +64,6 @@ using RiscvISAInst::MaxInstSrcRegs;
using RiscvISAInst::MaxInstDestRegs;
const int MaxMiscDestRegs = 1;
typedef uint8_t CCReg; // Not applicable to Riscv
// Not applicable to RISC-V
using VecElem = ::DummyVecElem;
using VecReg = ::DummyVecReg;

3
src/arch/sparc/registers.hh
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@@ -46,9 +46,6 @@ using SparcISAInst::MaxInstSrcRegs;
using SparcISAInst::MaxInstDestRegs;
using SparcISAInst::MaxMiscDestRegs;
// dummy typedef since we don't have CC regs
typedef uint8_t CCReg;
// Not applicable to SPARC
using VecElem = ::DummyVecElem;
using VecReg = ::DummyVecReg;

2
src/arch/x86/registers.hh
View File

@@ -96,8 +96,6 @@ const int FramePointerReg = INTREG_RBP;
// value
const int SyscallPseudoReturnReg = INTREG_RDX;
typedef uint64_t CCReg;
// Not applicable to x86
using VecElem = ::DummyVecElem;
using VecReg = ::DummyVecReg;

2
src/cpu/base_dyn_inst.hh
View File

@@ -662,7 +662,7 @@ class BaseDynInst : public ExecContext, public RefCounted
}
/** Records a CC register being set to a value. */
void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
void setCCRegOperand(const StaticInst *si, int idx, RegVal val)
{
setScalarResult(val);
}

4
src/cpu/checker/cpu.hh
View File

@@ -320,7 +320,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
return thread->getWritableVecPredReg(reg);
}
CCReg
RegVal
readCCRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->srcRegIdx(idx);
@@ -379,7 +379,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
}
void
setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isCCReg());

8
src/cpu/checker/thread_context.hh
View File

@@ -269,7 +269,7 @@ class CheckerThreadContext : public ThreadContext
VecPredRegContainer& getWritableVecPredReg(const RegId& reg) override
{ return actualTC->getWritableVecPredReg(reg); }
CCReg readCCReg(int reg_idx)
RegVal readCCReg(int reg_idx)
{ return actualTC->readCCReg(reg_idx); }
void
@@ -308,7 +308,7 @@ class CheckerThreadContext : public ThreadContext
}
void
setCCReg(int reg_idx, CCReg val)
setCCReg(int reg_idx, RegVal val)
{
actualTC->setCCReg(reg_idx, val);
checkerTC->setCCReg(reg_idx, val);
@@ -450,10 +450,10 @@ class CheckerThreadContext : public ThreadContext
void setVecPredRegFlat(int idx, const VecPredRegContainer& val) override
{ actualTC->setVecPredRegFlat(idx, val); }
CCReg readCCRegFlat(int idx)
RegVal readCCRegFlat(int idx)
{ return actualTC->readCCRegFlat(idx); }
void setCCRegFlat(int idx, CCReg val)
void setCCRegFlat(int idx, RegVal val)
{ actualTC->setCCRegFlat(idx, val); }
};

6
src/cpu/exec_context.hh
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@@ -74,7 +74,6 @@ class ExecContext {
public:
typedef TheISA::PCState PCState;
typedef TheISA::CCReg CCReg;
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
using VecPredRegContainer = TheISA::VecPredRegContainer;
@@ -189,8 +188,9 @@ class ExecContext {
* @{
* @name Condition Code Registers
*/
virtual CCReg readCCRegOperand(const StaticInst *si, int idx) = 0;
virtual void setCCRegOperand(const StaticInst *si, int idx, CCReg val) = 0;
virtual RegVal readCCRegOperand(const StaticInst *si, int idx) = 0;
virtual void setCCRegOperand(
const StaticInst *si, int idx, RegVal val) = 0;
/** @} */
/**

4
src/cpu/minor/exec_context.hh
View File

@@ -401,7 +401,7 @@ class ExecContext : public ::ExecContext
thread.getDTBPtr()->demapPage(vaddr, asn);
}
TheISA::CCReg
RegVal
readCCRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->srcRegIdx(idx);
@@ -410,7 +410,7 @@ class ExecContext : public ::ExecContext
}
void
setCCRegOperand(const StaticInst *si, int idx, TheISA::CCReg val) override
setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isCCReg());

8
src/cpu/o3/cpu.cc
View File

@@ -1379,7 +1379,7 @@ FullO3CPU<Impl>::getWritableVecPredReg(PhysRegIdPtr phys_reg)
}
template <class Impl>
CCReg
RegVal
FullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg)
{
ccRegfileReads++;
@@ -1429,7 +1429,7 @@ FullO3CPU<Impl>::setVecPredReg(PhysRegIdPtr phys_reg,
template <class Impl>
void
FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, CCReg val)
FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, RegVal val)
{
ccRegfileWrites++;
regFile.setCCReg(phys_reg, val);
@@ -1508,7 +1508,7 @@ FullO3CPU<Impl>::getWritableArchVecPredReg(int reg_idx, ThreadID tid)
}
template <class Impl>
CCReg
RegVal
FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
{
ccRegfileReads++;
@@ -1572,7 +1572,7 @@ FullO3CPU<Impl>::setArchVecPredReg(int reg_idx, const VecPredRegContainer& val,
template <class Impl>
void
FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
FullO3CPU<Impl>::setArchCCReg(int reg_idx, RegVal val, ThreadID tid)
{
ccRegfileWrites++;
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(

8
src/cpu/o3/cpu.hh
View File

@@ -463,7 +463,7 @@ class FullO3CPU : public BaseO3CPU
VecPredRegContainer& getWritableVecPredReg(PhysRegIdPtr reg_idx);
TheISA::CCReg readCCReg(PhysRegIdPtr phys_reg);
RegVal readCCReg(PhysRegIdPtr phys_reg);
void setIntReg(PhysRegIdPtr phys_reg, RegVal val);
@@ -475,7 +475,7 @@ class FullO3CPU : public BaseO3CPU
void setVecPredReg(PhysRegIdPtr reg_idx, const VecPredRegContainer& val);
void setCCReg(PhysRegIdPtr phys_reg, TheISA::CCReg val);
void setCCReg(PhysRegIdPtr phys_reg, RegVal val);
RegVal readArchIntReg(int reg_idx, ThreadID tid);
@@ -514,7 +514,7 @@ class FullO3CPU : public BaseO3CPU
VecPredRegContainer& getWritableArchVecPredReg(int reg_idx, ThreadID tid);
TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid);
RegVal readArchCCReg(int reg_idx, ThreadID tid);
/** Architectural register accessors. Looks up in the commit
* rename table to obtain the true physical index of the
@@ -533,7 +533,7 @@ class FullO3CPU : public BaseO3CPU
void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
const VecElem& val, ThreadID tid);
void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid);
void setArchCCReg(int reg_idx, RegVal val, ThreadID tid);
/** Sets the commit PC state of a specific thread. */
void pcState(const TheISA::PCState &newPCState, ThreadID tid);

6
src/cpu/o3/dyn_inst.hh
View File

@@ -66,7 +66,6 @@ class BaseO3DynInst : public BaseDynInst<Impl>
/** Binary machine instruction type. */
typedef TheISA::MachInst MachInst;
/** Register types. */
typedef TheISA::CCReg CCReg;
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg;
@@ -378,7 +377,8 @@ class BaseO3DynInst : public BaseDynInst<Impl>
return this->cpu->getWritableVecPredReg(this->_destRegIdx[idx]);
}
CCReg readCCRegOperand(const StaticInst *si, int idx)
RegVal
readCCRegOperand(const StaticInst *si, int idx)
{
return this->cpu->readCCReg(this->_srcRegIdx[idx]);
}
@@ -424,7 +424,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
BaseDynInst<Impl>::setVecPredRegOperand(si, idx, val);
}
void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
void setCCRegOperand(const StaticInst *si, int idx, RegVal val)
{
this->cpu->setCCReg(this->_destRegIdx[idx], val);
BaseDynInst<Impl>::setCCRegOperand(si, idx, val);

7
src/cpu/o3/regfile.hh
View File

@@ -65,7 +65,6 @@ class PhysRegFile
{
private:
typedef TheISA::CCReg CCReg;
using VecElem = TheISA::VecElem;
using VecRegContainer = TheISA::VecRegContainer;
using PhysIds = std::vector<PhysRegId>;
@@ -95,7 +94,7 @@ class PhysRegFile
std::vector<PhysRegId> vecPredRegIds;
/** Condition-code register file. */
std::vector<CCReg> ccRegFile;
std::vector<RegVal> ccRegFile;
std::vector<PhysRegId> ccRegIds;
/** Misc Reg Ids */
@@ -290,7 +289,7 @@ class PhysRegFile
}
/** Reads a condition-code register. */
CCReg
RegVal
readCCReg(PhysRegIdPtr phys_reg)
{
assert(phys_reg->isCCPhysReg());
@@ -365,7 +364,7 @@ class PhysRegFile
/** Sets a condition-code register to the given value. */
void
setCCReg(PhysRegIdPtr phys_reg, CCReg val)
setCCReg(PhysRegIdPtr phys_reg, RegVal val)
{
assert(phys_reg->isCCPhysReg());

10
src/cpu/o3/thread_context.hh
View File

@@ -271,7 +271,9 @@ class O3ThreadContext : public ThreadContext
return getWritableVecPredRegFlat(flattenRegId(id).index());
}
virtual CCReg readCCReg(int reg_idx) {
virtual RegVal
readCCReg(int reg_idx)
{
return readCCRegFlat(flattenRegId(RegId(CCRegClass,
reg_idx)).index());
}
@@ -310,7 +312,7 @@ class O3ThreadContext : public ThreadContext
}
virtual void
setCCReg(int reg_idx, CCReg val)
setCCReg(int reg_idx, RegVal val)
{
setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val);
}
@@ -424,8 +426,8 @@ class O3ThreadContext : public ThreadContext
virtual void setVecPredRegFlat(int idx,
const VecPredRegContainer& val) override;
virtual CCReg readCCRegFlat(int idx);
virtual void setCCRegFlat(int idx, CCReg val);
virtual RegVal readCCRegFlat(int idx);
virtual void setCCRegFlat(int idx, RegVal val);
};
#endif

4
src/cpu/o3/thread_context_impl.hh
View File

@@ -247,7 +247,7 @@ O3ThreadContext<Impl>::getWritableVecPredRegFlat(int reg_id)
}
template <class Impl>
TheISA::CCReg
RegVal
O3ThreadContext<Impl>::readCCRegFlat(int reg_idx)
{
return cpu->readArchCCReg(reg_idx, thread->threadId());
@@ -301,7 +301,7 @@ O3ThreadContext<Impl>::setVecPredRegFlat(int reg_idx,
template <class Impl>
void
O3ThreadContext<Impl>::setCCRegFlat(int reg_idx, TheISA::CCReg val)
O3ThreadContext<Impl>::setCCRegFlat(int reg_idx, RegVal val)
{
cpu->setArchCCReg(reg_idx, val, thread->threadId());

5
src/cpu/simple/exec_context.hh
View File

@@ -60,7 +60,6 @@ class BaseSimpleCPU;
class SimpleExecContext : public ExecContext {
protected:
typedef TheISA::CCReg CCReg;
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
@@ -365,7 +364,7 @@ class SimpleExecContext : public ExecContext {
thread->setVecPredReg(reg, val);
}
CCReg
RegVal
readCCRegOperand(const StaticInst *si, int idx) override
{
numCCRegReads++;
@@ -375,7 +374,7 @@ class SimpleExecContext : public ExecContext {
}
void
setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
{
numCCRegWrites++;
const RegId& reg = si->destRegIdx(idx);

16
src/cpu/simple_thread.hh
View File

@@ -100,7 +100,6 @@ class SimpleThread : public ThreadState
{
protected:
typedef TheISA::MachInst MachInst;
typedef TheISA::CCReg CCReg;
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
using VecPredRegContainer = TheISA::VecPredRegContainer;
@@ -113,7 +112,7 @@ class SimpleThread : public ThreadState
VecRegContainer vecRegs[TheISA::NumVecRegs];
VecPredRegContainer vecPredRegs[TheISA::NumVecPredRegs];
#ifdef ISA_HAS_CC_REGS
TheISA::CCReg ccRegs[TheISA::NumCCRegs];
RegVal ccRegs[TheISA::NumCCRegs];
#endif
TheISA::ISA *const isa; // one "instance" of the current ISA.
@@ -379,7 +378,8 @@ class SimpleThread : public ThreadState
return regVal;
}
CCReg readCCReg(int reg_idx)
RegVal
readCCReg(int reg_idx)
{
#ifdef ISA_HAS_CC_REGS
int flatIndex = isa->flattenCCIndex(reg_idx);
@@ -449,7 +449,7 @@ class SimpleThread : public ThreadState
}
void
setCCReg(int reg_idx, CCReg val)
setCCReg(int reg_idx, RegVal val)
{
#ifdef ISA_HAS_CC_REGS
int flatIndex = isa->flattenCCIndex(reg_idx);
@@ -622,13 +622,13 @@ class SimpleThread : public ThreadState
}
#ifdef ISA_HAS_CC_REGS
CCReg readCCRegFlat(int idx) { return ccRegs[idx]; }
void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; }
RegVal readCCRegFlat(int idx) { return ccRegs[idx]; }
void setCCRegFlat(int idx, RegVal val) { ccRegs[idx] = val; }
#else
CCReg readCCRegFlat(int idx)
RegVal readCCRegFlat(int idx)
{ panic("readCCRegFlat w/no CC regs!\n"); }
void setCCRegFlat(int idx, CCReg val)
void setCCRegFlat(int idx, RegVal val)
{ panic("setCCRegFlat w/no CC regs!\n"); }
#endif
};

8
src/cpu/thread_context.cc
View File

@@ -108,8 +108,8 @@ ThreadContext::compare(ThreadContext *one, ThreadContext *two)
// loop through the Condition Code registers.
for (int i = 0; i < TheISA::NumCCRegs; ++i) {
TheISA::CCReg t1 = one->readCCReg(i);
TheISA::CCReg t2 = two->readCCReg(i);
RegVal t1 = one->readCCReg(i);
RegVal t2 = two->readCCReg(i);
if (t1 != t2)
panic("CC reg idx %d doesn't match, one: %#x, two: %#x",
i, t1, t2);
@@ -192,7 +192,7 @@ serialize(ThreadContext &tc, CheckpointOut &cp)
SERIALIZE_ARRAY(intRegs, NumIntRegs);
#ifdef ISA_HAS_CC_REGS
CCReg ccRegs[NumCCRegs];
RegVal ccRegs[NumCCRegs];
for (int i = 0; i < NumCCRegs; ++i)
ccRegs[i] = tc.readCCRegFlat(i);
SERIALIZE_ARRAY(ccRegs, NumCCRegs);
@@ -233,7 +233,7 @@ unserialize(ThreadContext &tc, CheckpointIn &cp)
tc.setIntRegFlat(i, intRegs[i]);
#ifdef ISA_HAS_CC_REGS
CCReg ccRegs[NumCCRegs];
RegVal ccRegs[NumCCRegs];
UNSERIALIZE_ARRAY(ccRegs, NumCCRegs);
for (int i = 0; i < NumCCRegs; ++i)
tc.setCCRegFlat(i, ccRegs[i]);

17
src/cpu/thread_context.hh
View File

@@ -95,7 +95,6 @@ class ThreadContext
{
protected:
typedef TheISA::MachInst MachInst;
typedef TheISA::CCReg CCReg;
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
using VecPredRegContainer = TheISA::VecPredRegContainer;
@@ -248,7 +247,7 @@ class ThreadContext
const = 0;
virtual VecPredRegContainer& getWritableVecPredReg(const RegId& reg) = 0;
virtual CCReg readCCReg(int reg_idx) = 0;
virtual RegVal readCCReg(int reg_idx) = 0;
virtual void setIntReg(int reg_idx, RegVal val) = 0;
@@ -261,7 +260,7 @@ class ThreadContext
virtual void setVecPredReg(const RegId& reg,
const VecPredRegContainer& val) = 0;
virtual void setCCReg(int reg_idx, CCReg val) = 0;
virtual void setCCReg(int reg_idx, RegVal val) = 0;
virtual TheISA::PCState pcState() = 0;
@@ -355,8 +354,8 @@ class ThreadContext
virtual void setVecPredRegFlat(int idx,
const VecPredRegContainer& val) = 0;
virtual CCReg readCCRegFlat(int idx) = 0;
virtual void setCCRegFlat(int idx, CCReg val) = 0;
virtual RegVal readCCRegFlat(int idx) = 0;
virtual void setCCRegFlat(int idx, RegVal val) = 0;
/** @} */
};
@@ -522,7 +521,7 @@ class ProxyThreadContext : public ThreadContext
VecPredRegContainer& getWritableVecPredReg(const RegId& reg)
{ return actualTC->getWritableVecPredReg(reg); }
CCReg readCCReg(int reg_idx)
RegVal readCCReg(int reg_idx)
{ return actualTC->readCCReg(reg_idx); }
void setIntReg(int reg_idx, RegVal val)
@@ -540,7 +539,7 @@ class ProxyThreadContext : public ThreadContext
void setVecElem(const RegId& reg, const VecElem& val)
{ actualTC->setVecElem(reg, val); }
void setCCReg(int reg_idx, CCReg val)
void setCCReg(int reg_idx, RegVal val)
{ actualTC->setCCReg(reg_idx, val); }
TheISA::PCState pcState() { return actualTC->pcState(); }
@@ -622,10 +621,10 @@ class ProxyThreadContext : public ThreadContext
void setVecPredRegFlat(int idx, const VecPredRegContainer& val)
{ actualTC->setVecPredRegFlat(idx, val); }
CCReg readCCRegFlat(int idx)
RegVal readCCRegFlat(int idx)
{ return actualTC->readCCRegFlat(idx); }
void setCCRegFlat(int idx, CCReg val)
void setCCRegFlat(int idx, RegVal val)
{ actualTC->setCCRegFlat(idx, val); }
};