Javier Setoain 2e47c6c5ed arch-arm: Add support for SVE load/store structures ...

Change-Id: I4d9cde18dfc3d478eacc156de6a4a9721eb9e2ff
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13524
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

2019-07-27 20:51:31 +00:00

..

alpha

arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy.

2019-05-30 14:20:03 +00:00

arm

arch-arm: Add support for SVE load/store structures

2019-07-27 20:51:31 +00:00

generic

arch, base, sim: Replace Copy(String)?(In|Out) with equivalent code.

2019-05-30 06:07:33 +00:00

hsail

arch-hsail: changed gen.py shebang from python(3) to python2.7

2019-03-11 22:13:24 +00:00

mips

arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy.

2019-05-30 14:20:03 +00:00

null

cpu, arch: Replace the CCReg type with RegVal.

2019-02-01 01:22:19 +00:00

power

arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy.

2019-05-30 14:20:03 +00:00

riscv

arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy.

2019-05-30 14:20:03 +00:00

sparc

arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy.

2019-05-30 14:20:03 +00:00

x86

arch-x86: Don't free PTW state with inflight requests

2019-07-22 14:33:01 +00:00

isa_parser.py

arch: Add include guards to auto-gen. decode header

2019-05-30 15:56:17 +00:00

micro_asm_test.py

scons: Switch from the print statement to the print function.

2018-03-06 23:39:01 +00:00

micro_asm.py

scons: Switch from the print statement to the print function.

2018-03-06 23:39:01 +00:00

SConscript

arch: Remove the mt.hh switching header.

2019-04-30 16:27:17 +00:00