Giacomo Travaglini 2242196f03 arch-arm: Fix assert fail when UQRSHL shiftAmt==0 (#75) ...

When shiftAmt is 0 for a UQRSHL instruction, the code called bits() with
incorrect arguments. This fixes a left-shift of 0 to be a NOP/mov, as
required.

Change-Id: Ic86ca40ac42bfb767a09e8c65a53cec56382a008

Co-authored-by: Marton Erdos <marton.erdos@arm.com>

2023-07-18 21:08:29 -07:00

..

amdgpu

dev-amdgpu: Add missing 'overrides'

2023-07-10 13:39:52 -07:00

arm

arch-arm: Fix assert fail when UQRSHL shiftAmt==0 (#75)

2023-07-18 21:08:29 -07:00

generic

arch-riscv: fix load reserved store conditional

2023-06-16 16:44:49 +00:00

isa_parser

arch: set multiline re as default in isa_parser

2023-07-18 20:46:22 -07:00

mips

arch,base,dev,sim: Convert objects to use the HostSocket param type.

2023-04-12 02:18:22 +00:00

null

misc: Replace TARGET_ISA with USE_${ISA} variables.

2022-09-02 10:20:51 +00:00

power

arch,base,dev,sim: Convert objects to use the HostSocket param type.

2023-04-12 02:18:22 +00:00

riscv

arch-riscv: Check FPU status for c.flwsp c.fldsp c.fswsp c.fsdsp

2023-07-18 20:41:22 -07:00

sparc

misc: Fix 'unused variable' clang errors with gem5.fast

2023-05-08 22:54:06 +00:00

x86

arch-x86: Fix CPUID function 0

2023-05-25 14:38:09 +00:00

micro_asm_test.py

misc: Use python f-strings for string formatting

2023-03-16 09:05:29 +00:00

micro_asm.py

misc: Use python f-strings for string formatting

2023-03-16 09:05:29 +00:00

SConscript

arch,cpu: Add boilerplate support for matrix registers

2023-01-17 10:09:56 +00:00

SConsopts

misc: Replace TARGET_ISA with USE_${ISA} variables.

2022-09-02 10:20:51 +00:00