Giacomo Travaglini 2242196f03 arch-arm: Fix assert fail when UQRSHL shiftAmt==0 (#75) ...

When shiftAmt is 0 for a UQRSHL instruction, the code called bits() with
incorrect arguments. This fixes a left-shift of 0 to be a NOP/mov, as
required.

Change-Id: Ic86ca40ac42bfb767a09e8c65a53cec56382a008

Co-authored-by: Marton Erdos <marton.erdos@arm.com>

2023-07-18 21:08:29 -07:00

..

arch

arch-arm: Fix assert fail when UQRSHL shiftAmt==0 (#75)

2023-07-18 21:08:29 -07:00

base

misc: Update version to v23.0.0.1

2023-07-10 14:08:27 -07:00

cpu

gpu-compute: Remove use of 'std::random_shuffle'

2023-07-10 13:39:52 -07:00

dev

dev: Warn when resp packet is error in dma port

2023-07-18 20:57:19 -07:00

doc

misc: Removed unneeded Doxygen pages

2020-04-25 01:08:38 +00:00

doxygen

base,misc: Add group definitions for newly tagged API in src/base

2020-09-08 22:29:43 +00:00

gpu-compute

gpu-compute: Add missing include in dispatcher.cc

2023-07-10 13:42:47 -07:00

kern

misc: Remove the FreeBSD namespace

2023-01-17 09:16:20 +00:00

learning_gem5

mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner

2023-02-03 06:11:45 +00:00

mem

mem: port: add TracingExtension for debug purpose

2023-07-18 20:50:19 -07:00

proto

misc: Run pre-commit run on all files in repo

2022-08-24 21:47:07 +00:00

python

python: Fix namespaced enums params code generation

2023-07-18 21:01:19 -07:00

sim

base: Output link to common errors page

2023-05-26 04:42:25 +00:00

sst

mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner

2023-02-03 06:11:45 +00:00

systemc

misc: Use python f-strings for string formatting

2023-03-16 09:05:29 +00:00

Doxyfile

misc: Update version to v23.0.0.1

2023-07-10 14:08:27 -07:00

SConscript

scons,stdlib: Remove deprecated 'distutils' module

2023-06-15 20:14:55 +00:00