Giacomo Travaglini 1cfaa8da83 arch-arm: Remove unimplemented miscreg handling in MSR imm ...

The checkFaultAccessAArch64SysReg function is now in charge
of returning the Undefined Instruction fault for unimplemented
registers

Change-Id: I75c00c6fbce33d1729a4923eae585260a8461db3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61971
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2022-08-02 20:45:51 +00:00

..

amdgpu

gpu-compute,arch-vega: Overhaul HWRegs, setreg, getreg

2022-07-28 14:10:33 +00:00

arm

arch-arm: Remove unimplemented miscreg handling in MSR imm

2022-08-02 20:45:51 +00:00

generic

arch,cpu: Store pointers to RegClass-es instead of instances.

2022-07-26 19:37:59 +00:00

isa_parser

arch,cpu,sim: Store registers in InstRecord with InstResult.

2022-08-02 12:44:25 +00:00

mips

arch,cpu,sim: Store registers in InstRecord with InstResult.

2022-08-02 12:44:25 +00:00

null

arch: Remove TheISA::VecElem from arch/vecregs.hh.

2022-02-01 18:48:55 +00:00

power

arch,cpu,sim: Store registers in InstRecord with InstResult.

2022-08-02 12:44:25 +00:00

riscv

cpu,arch: Put the name of the RegClass into the RegClass.

2022-07-29 19:30:51 +00:00

sparc

arch,cpu,sim: Store registers in InstRecord with InstResult.

2022-08-02 12:44:25 +00:00

x86

cpu,arch: Put the name of the RegClass into the RegClass.

2022-07-29 19:30:51 +00:00

micro_asm_test.py

arch:arch-x86: Fix style of some classes in the ucode assembler.

2022-03-19 13:37:33 +00:00

micro_asm.py

arch:arch-x86: Fix style of some classes in the ucode assembler.

2022-03-19 13:37:33 +00:00

SConscript

scons: Put all config variables in an env['CONF'] sub-dict.

2022-03-28 20:31:21 +00:00

SConsopts

scons: Make all sticky variables automatically exported.

2022-03-15 00:45:30 +00:00