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gem5/src/dev
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Gabe Black 43114ad1dd dev: Use regular atomic accesses for DMA in bypass mode. 
These are now accelerated with backdoor accesses and should be at least
as fast as functional accesses. This removes a dependency on port
proxies, and also stops the HDLCD from using functional accesses.

Change-Id: I5e959288eb533d09cffa7b79938aa2f61e4aff7d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38720
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-01-13 01:29:32 +00:00
..
arm
dev-arm: SMMUv3, enable interrupt interface
2021-01-07 09:07:09 +00:00
hsa
dev-hsa,gpu-compute: Agent Packet handler implemented.
2020-11-16 16:12:48 +00:00
i2c
misc: Delete the now unnecessary create methods.
2020-10-30 04:00:20 +00:00
mips
misc: Delete the now unnecessary create methods.
2020-10-30 04:00:20 +00:00
net
dev,stats: Update stats style of src/dev/net
2020-11-19 22:46:48 +00:00
pci
dev,stats: Update stats style for CopyEngine and IdeDisk
2020-11-19 22:46:48 +00:00
ps2
misc: Delete the now unnecessary create methods.
2020-10-30 04:00:20 +00:00
serial
dev: Use BitUnions and a RegisterBank in the Uart8250.
2020-12-18 00:30:55 +00:00
sparc
misc: Delete the now unnecessary create methods.
2020-10-30 04:00:20 +00:00
storage
dev,stats: Update stats style for CopyEngine and IdeDisk
2020-11-19 22:46:48 +00:00
virtio
misc: Delete the now unnecessary create methods.
2020-10-30 04:00:20 +00:00
x86
dev: Convert the x86 i8237 DMA controller to use RegBank.
2020-11-03 02:04:49 +00:00
baddev.cc
misc: Delete the now unnecessary create methods.
2020-10-30 04:00:20 +00:00
baddev.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
BadDevice.py
dev: Delete the authors list from files in src/dev.
2020-02-18 03:34:01 +00:00
Device.py
dev: Use generateFdtProperty in the PioDevice
2020-10-17 10:21:08 +00:00
dma_device.cc
dev: Use regular atomic accesses for DMA in bypass mode.
2021-01-13 01:29:32 +00:00
dma_device.hh
dev: Use regular atomic accesses for DMA in bypass mode.
2021-01-13 01:29:32 +00:00
intel_8254_timer.cc
dev: Delete the authors list from files in src/dev.
2020-02-18 03:34:01 +00:00
intel_8254_timer.hh
sim,mem,dev: Merge eventq_impl.hh into eventq.hh.
2020-06-04 01:54:19 +00:00
intpin.cc
dev: Delete the authors list from files in src/dev.
2020-02-18 03:34:01 +00:00
intpin.hh
dev: Delete the authors list from files in src/dev.
2020-02-18 03:34:01 +00:00
IntPin.py
dev: Delete the authors list from files in src/dev.
2020-02-18 03:34:01 +00:00
io_device.cc
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
io_device.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
isa_fake.cc
misc: Delete the now unnecessary create methods.
2020-10-30 04:00:20 +00:00
isa_fake.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
mc146818.cc
dev: Delete the authors list from files in src/dev.
2020-02-18 03:34:01 +00:00
mc146818.hh
sim,mem,dev: Merge eventq_impl.hh into eventq.hh.
2020-06-04 01:54:19 +00:00
pixelpump.cc
dev: Delete the authors list from files in src/dev.
2020-02-18 03:34:01 +00:00
pixelpump.hh
dev: Fix style in the pixel pump base class.
2021-01-06 04:26:33 +00:00
platform.cc
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
platform.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
Platform.py
dev: Delete the authors list from files in src/dev.
2020-02-18 03:34:01 +00:00
reg_bank.hh
dev: Add a new RegisterBank which helps handle device registers.
2020-11-01 13:08:26 +00:00
reg_bank.test.cc
dev: -Wdeprecated-copy not available on all supported compilers
2020-11-25 09:43:24 +00:00
rtcreg.h
dev: Delete the authors list from files in src/dev.
2020-02-18 03:34:01 +00:00
SConscript
dev: Add a new RegisterBank which helps handle device registers.
2020-11-01 13:08:26 +00:00