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gem5/src/mem
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Richard Cooper f9b57ee4ed mem-ruby: Allow SLICC symbols to have no description. 
Updated the SLICC `Symbol` class to return an empty string when its
`desc` property is read.

The SLICC language does not require a symbol to have a `desc` for
protocol generation, but the generation of SLICC HTML documentation
expects a `desc` and will fail if it is not present.

Change-Id: I07cc0ab805520eb74f86c6ea8036abb7354b10a9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60870
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-07-06 17:09:46 +00:00
..
cache
mem-cache: Avoid calling .front() on a possibly empty std::list
2022-03-02 09:59:59 +00:00
probes
scons: Put all config variables in an env['CONF'] sub-dict.
2022-03-28 20:31:21 +00:00
protocol
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
qos
scons: Add sim_object and enums arguments to SimObject().
2021-12-08 08:01:23 +00:00
ruby
mem-ruby: Add descriptions to the CHI DVM symbols.
2022-07-06 17:09:46 +00:00
slicc
mem-ruby: Allow SLICC symbols to have no description.
2022-07-06 17:09:46 +00:00
abstract_mem.cc
arch,cpu,mem,sim: Fold arch/locked_mem.hh into the BaseISA class.
2021-09-28 19:56:01 +00:00
abstract_mem.hh
mem: Adopt a memory namespace for memories
2021-07-09 11:24:10 +00:00
AbstractMemory.py
mem: Adopt a memory namespace for memories
2021-07-09 11:24:10 +00:00
addr_mapper.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
addr_mapper.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
AddrMapper.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
backdoor.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
bridge.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
bridge.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
Bridge.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
cfi_mem.cc
mem: Fix for CFI memory
2021-09-20 08:00:53 +00:00
cfi_mem.hh
mem: Fix for CFI memory
2021-09-20 08:00:53 +00:00
CfiMemory.py
mem: Adopt a memory namespace for memories
2021-07-09 11:24:10 +00:00
coherent_xbar.cc
misc: Replace the GEM5_VAR_USED macro with [[maybe_unused]].
2021-07-29 10:17:51 +00:00
coherent_xbar.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
comm_monitor.cc
misc: Remove sim/cur_tick dependency from sim/core.hh
2021-07-06 09:59:11 +00:00
comm_monitor.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
CommMonitor.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
dram_interface.cc
mem: Support for separate tRCD and tCL for reads/writes
2022-06-06 18:31:06 +00:00
dram_interface.hh
mem: Support for separate tRCD and tCL for reads/writes
2022-06-06 18:31:06 +00:00
DRAMInterface.py
mem: Add HBM2 pseudo channel interface configuration
2022-06-06 18:31:06 +00:00
drampower.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
drampower.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
dramsim2_wrapper.cc
misc: Replace the GEM5_VAR_USED macro with [[maybe_unused]].
2021-07-29 10:17:51 +00:00
dramsim2_wrapper.hh
mem: Adopt a memory namespace for memories
2021-07-09 11:24:10 +00:00
dramsim2.cc
mem: Adopt a memory namespace for memories
2021-07-09 11:24:10 +00:00
dramsim2.hh
mem: Adopt a memory namespace for memories
2021-07-09 11:24:10 +00:00
dramsim3_wrapper.cc
misc: Replace the GEM5_VAR_USED macro with [[maybe_unused]].
2021-07-29 10:17:51 +00:00
dramsim3_wrapper.hh
mem: Adopt a memory namespace for memories
2021-07-09 11:24:10 +00:00
dramsim3.cc
mem: Adopt a memory namespace for memories
2021-07-09 11:24:10 +00:00
dramsim3.hh
mem: Adopt a memory namespace for memories
2021-07-09 11:24:10 +00:00
DRAMsim3.py
mem: Adopt a memory namespace for memories
2021-07-09 11:24:10 +00:00
DRAMSim2.py
mem: Adopt a memory namespace for memories
2021-07-09 11:24:10 +00:00
external_master.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
external_master.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
external_slave.cc
misc: Replace the GEM5_VAR_USED macro with [[maybe_unused]].
2021-07-29 10:17:51 +00:00
external_slave.hh
mem: Stop using SlavePort as a base class.
2021-10-13 20:28:05 +00:00
ExternalMaster.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
ExternalSlave.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
hbm_ctrl.cc
mem: Add an HBM memory controller
2022-06-06 18:31:06 +00:00
hbm_ctrl.hh
mem: Add an HBM memory controller
2022-06-06 18:31:06 +00:00
HBMCtrl.py
mem: Add support for min reads per switch
2022-06-06 18:31:06 +00:00
hetero_mem_ctrl.cc
mem: Add an HBM memory controller
2022-06-06 18:31:06 +00:00
hetero_mem_ctrl.hh
mem: Add an HBM memory controller
2022-06-06 18:31:06 +00:00
HeteroMemCtrl.py
mem: Split memory controller into base MemCtrl and HeteroMemCtrl
2022-06-06 18:31:06 +00:00
hmc_controller.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
hmc_controller.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
HMCController.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
htm.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
htm.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
mem_checker_monitor.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
mem_checker_monitor.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
mem_checker.cc
mem,sim: Replace the deprecated chatty_assert with gem5_assert.
2021-08-21 00:54:54 +00:00
mem_checker.hh
misc: Remove sim/cur_tick dependency from sim/core.hh
2021-07-06 09:59:11 +00:00
mem_ctrl.cc
mem: Add support for min reads per switch
2022-06-06 18:31:06 +00:00
mem_ctrl.hh
mem: Add support for min reads per switch
2022-06-06 18:31:06 +00:00
mem_delay.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
mem_delay.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
mem_interface.cc
mem: Add an HBM memory controller
2022-06-06 18:31:06 +00:00
mem_interface.hh
mem: Add an HBM memory controller
2022-06-06 18:31:06 +00:00
mem_requestor.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
MemChecker.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
MemCtrl.py
mem: Add support for min reads per switch
2022-06-06 18:31:06 +00:00
MemDelay.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
MemInterface.py
mem: Adopt a memory namespace for memories
2021-07-09 11:24:10 +00:00
multi_level_page_table.hh
misc: Move MemPool based calls to the SEWorkload.
2021-09-21 02:05:32 +00:00
noncoherent_xbar.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
noncoherent_xbar.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
nvm_interface.cc
mem: Add an HBM memory controller
2022-06-06 18:31:06 +00:00
nvm_interface.hh
mem: Add an HBM memory controller
2022-06-06 18:31:06 +00:00
NVMInterface.py
mem: Split memory controller into base MemCtrl and HeteroMemCtrl
2022-06-06 18:31:06 +00:00
packet_access.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
packet_queue.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
packet_queue.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
packet.cc
mem: Add TlbiExtSync packet type
2022-03-15 16:20:49 +00:00
packet.hh
mem: Add TlbiExtSync packet type
2022-03-15 16:20:49 +00:00
page_table.cc
mem: Add a translation generator function to EmulationPageTable.
2021-10-22 21:43:02 +00:00
page_table.hh
mem: Add a translation generator function to EmulationPageTable.
2021-10-22 21:43:02 +00:00
physical.cc
mem: Align mmap offset to page boundary
2022-03-30 05:18:52 +00:00
physical.hh
mem: Align mmap offset to page boundary
2022-03-30 05:18:52 +00:00
port_proxy.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
port_proxy.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
port_terminator.cc
mem: Adding PortTerminator
2021-10-28 20:13:41 +00:00
port_terminator.hh
mem: Adding PortTerminator
2021-10-28 20:13:41 +00:00
port.cc
mem: Use debug trace instead of warn for default backdoor
2022-06-29 12:43:11 +00:00
port.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
PortTerminator.py
mem: Adding PortTerminator
2021-10-28 20:13:41 +00:00
qport.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
request.hh
mem: add clear modifiers for request flags
2022-05-24 00:50:00 +00:00
SConscript
mem: Use debug trace instead of warn for default backdoor
2022-06-29 12:43:11 +00:00
SConsopts
scons: Explicitly add librt to scons
2021-07-07 21:37:15 +00:00
se_translating_port_proxy.cc
mem: Use the MMU's translation generator in translating proxies.
2021-10-22 21:43:02 +00:00
se_translating_port_proxy.hh
mem: Use the MMU's translation generator in translating proxies.
2021-10-22 21:43:02 +00:00
serial_link.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
serial_link.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
SerialLink.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
shared_memory_server.cc
mem: Add SharedMemoryServer
2022-03-28 08:26:44 +00:00
shared_memory_server.hh
mem: Add SharedMemoryServer
2022-03-28 08:26:44 +00:00
SharedMemoryServer.py
mem: Add SharedMemoryServer
2022-03-28 08:26:44 +00:00
simple_mem.cc
mem: Adopt a memory namespace for memories
2021-07-09 11:24:10 +00:00
simple_mem.hh
mem: Adopt a memory namespace for memories
2021-07-09 11:24:10 +00:00
SimpleMemory.py
mem: Adopt a memory namespace for memories
2021-07-09 11:24:10 +00:00
snoop_filter.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
snoop_filter.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
stack_dist_calc.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
stack_dist_calc.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
sys_bridge.cc
mem: Create a SysBridge object to bridge between Systems interconnect.
2022-03-10 04:03:39 +00:00
sys_bridge.hh
mem: Create a SysBridge object to bridge between Systems interconnect.
2022-03-10 04:03:39 +00:00
SysBridge.py
mem: Create a SysBridge object to bridge between Systems interconnect.
2022-03-10 04:03:39 +00:00
token_port.cc
misc: Remove AMD license addition
2021-12-11 04:00:56 +00:00
token_port.hh
misc: Remove AMD license addition
2021-12-11 04:00:56 +00:00
tport.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
tport.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
translating_port_proxy.cc
mem: Use the MMU's translation generator in translating proxies.
2021-10-22 21:43:02 +00:00
translating_port_proxy.hh
mem: Use the MMU's translation generator in translating proxies.
2021-10-22 21:43:02 +00:00
translation_gen.hh
mem: Add a translation gen helper class.
2021-10-14 20:49:23 +00:00
translation_gen.test.cc
ext: upgrade to googletest 1.11.x
2022-01-20 01:16:02 +00:00
xbar.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
xbar.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
XBar.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00