Commit Graph

15136 Commits

Author SHA1 Message Date
Daniel R. Carvalho
ffad8a370a base: Fix undefined behavior in mask generation
When generating a mask, if the number of bits is greater than
the maximum shift distance (63), the shift will have undefined
behavior. Previously the branch was taking care of a single
trespassing case, and it has been fixed to cover the remaining.

Issue-on: https://gem5.atlassian.net/browse/GEM5-205

Change-Id: Ib5a00917c8d2b23ffdb710c2f9673d956cd9f43e
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27104
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
2020-04-03 23:13:25 +00:00
Matthew Poremba
64134b6e66 base,arch-hsail: Fix GPU build
The GPU build is currently broken due to recent changes. This fixes
the build after changes to local access, removal of getSyscallArg,
and creating of AMO header in base.

Change-Id: I43506f6fb0a92a61a50ecb9efa7ee279ecb21d98
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27136
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
2020-04-03 21:51:57 +00:00
Gabe Black
7e303da76f scons: Fix an exception in the DictImporter on scons shutdown.
The DictImporter's __del__ method calls unload, and that imports
sys.modules so that it can remove the modules that the DictImporter had
set up as the importer goes away.

Unfortunately, the importer only goes away when python is shutting down,
and at that time some aspects of the system, namely sys.meta_path, have
been cleaned up. When unload tries to import sys, that causes an
exception which scons/python reports but which doesn't do anything bad
otherwise.

In all of the examples of this older style of import object online, none
had a __del__ method, and none worried about cleaning up sys.modules
when they went away. In light of that, I've removed the __del__ method
entirely.

Another reason I think it's safe to remove __del__ is that the importer
was not actually being deleted even when it was removed from
sys.meta_path, and all the modules it had loaded where removed from
sys.modules. I think that was because the SimObject classes that it had
set up still had references (they are used later in the SConscript), and
those would, either directly or indirectly, refer back to the modules
and the importer. Those remaining references kept the importer alive,
preventing __del__ from being called before all those other objects were
cleaned up.

I think in python 2, the order things were cleaned up just so happened
to avoid trying to import sys when it was no longer possible, but in
python 3 that changed and resulted in this exception being thrown.

I've tried building gem5 with scons running under python 2 and python 3,
and with this change there is no error at shutdown. Both also produce a
gem5 binary which can run hello world without problems.

Change-Id: Ib1f5c7403df57fc420cec7ec0fef20a164a06991
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27247
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2020-04-02 22:25:07 +00:00
Nikos Nikoleris
fa3119bfc3 arch-arm: Add missing include in QARMA implementation
Change-Id: Ic8a0146968d45ab1007687686eb73639a1c85513
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27407
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
2020-04-02 13:31:59 +00:00
Giacomo Travaglini
303663d5c9 configs: Enabling SimObj CLI for baremetal platform
Change-Id: I0d4059976c8fb6a1d796998af302eaa764609f86
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27347
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-01 16:06:54 +00:00
Gabe Black
0d0979ba17 util: Update jni_gem5Op.c so it will compile again.
The header for the m5op entry points had moved. Also the names of the
entry points had been normalized to have a consistent structure. Neither
of those changes were ported to this file, making it no longer compile.

Change-Id: I890c0486bd19fe2692cce92983290e854dc87afa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27211
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2020-04-01 11:58:06 +00:00
Gabe Black
031d261fe1 util: Update the m5 util Makefiles to not use javah.
In more recent versions of the JDK, the javah tool has been dropped. The
same job can be accomplished by passing a -h option to javac, telling it
where to put the header files javah would have generated.

Change-Id: Ibc543d5fa222848458f45b1945f8050b85b77ca2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27210
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2020-04-01 11:58:06 +00:00
Gabe Black
a959f28ec9 util: Move source files into a src directory.
This also moves the Makefiles, which will still produce build output in
the src directory. This is to prepare for a scons based build system
which will create a separate build directory with build artifacts.

Change-Id: I7c6d325e1d0a428656b2e3070b5e942515543696
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27209
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2020-04-01 11:58:06 +00:00
Gabe Black
547c152609 util,x86: Use M5OP_FOREACH to define the m5op entry points for x86.
Change-Id: Idbfa3341a5e0d2cf57ce7dbe8cf45834b3aa067a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27208
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2020-04-01 11:58:06 +00:00
Gabe Black
27047499d4 util,sparc: Use M5OP_FOREACH to define the m5op entry points for sparc.
Change-Id: I9b125c843425ef4a7a59061d5897dd8e83e06abb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27207
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2020-04-01 11:58:06 +00:00
Gabe Black
81950ca847 util: Undef M5OP at the end of assembly files that use M5OP_FOREACH.
This may not be necessary since M5OP is defined/used at the end of the
function, but it's best to clean up after ourselves.

Change-Id: I524d92cb8dc44c6004dfa8109f3b17f56dba763e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27206
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2020-04-01 11:58:06 +00:00
Gabe Black
1030dfd56e util: Remove the subfunc arg from M5OP_FOREACH.
Now that the annotation pseudo ops are removed, the subfunction is
always zero. It is no longer decoded within gem5 either. The format of
the pseudo op func/subfunc mechanism is unchanged for compatibility, but
the subfunc field will always be zero now.

Change-Id: I2167571577b6557d06aa26d8aecaca78797f5f59
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27205
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2020-03-31 22:19:29 +00:00
Gabe Black
649e1faec9 misc: Remove the now unused M5OP_FOREACH_ANNOTATION macro.
Change-Id: I33827c923cf02c94fea2df972919636961f3dd94
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27204
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2020-03-31 22:19:29 +00:00
Adrian Herrera
9bcffd1e29 arch-arm, dev-arm: WakeRequest implementation
This patch provides a GIC WakeRequest implementation based on GICv3 and
FVPBasePwrCtrl models. When GICR_WAKER.ProcessorSleep is set to 1 for a
certain PE, any pending interrupt coming from the Redistributor asserts
a WakeRequest signal; if PwrStatus.WEN is set, this brings up the PE.

Change-Id: I5e8b7f0e9f7706dfcc7d2e0857f4c3b86cdc04ca
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26810
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2020-03-31 13:30:16 +00:00
Gabe Black
4122649122 util: Remove the annotation pseudo ops symbols from the m5 utility.
These pseudo ops have been removed and will no longer work with gem5.

Change-Id: Ie07a320db528cb5c628f2c194fb1672b1fcae39a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27203
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2020-03-31 12:07:40 +00:00
Boris Shingarov
e037a93eae configs: Add --wait-gdb as option to se.py
I switch between waiting and non-waiting scenario many times per day.
The BaseCPU.wait_for_remote_gdb attribute, introduced in c2baaab0ed,
makes it much less painful by saving many recompiles.
The present commit tries to go a bit further: the se.py script is
under version control, and changing it interferes with smooth git
workflow.

Change-Id: Ie65ffc44b11d78d5e7878f81f2fcdafa143c20a8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27287
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-03-30 22:12:05 +00:00
Gabe Black
37a366e444 mem: Get rid of the now unused SecurePortProxy class.
This proxy was only used by the ARM semihosting interface which can now
use a tweaked regular TranslatingPortProxy or SETranslatingPortProxy
instead of this special purpose class.

This sort of class would still be necessary if you wanted to use
physical addresses and not virtual addresses, but presently there is no
such use. This code can be retrieved from history if it's needed in the
future.

Change-Id: Ie47a8b4bb173cba1a06bd3ca60391081987936b8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26625
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2020-03-30 21:47:20 +00:00
Gabe Black
89bb4f7e37 arm: Make semihosting use virtual addresses.
This is in accordance with the spec. To successfully translate requests
which need their secure flag set, build a translating port proxy with
that flag enabled.

Change-Id: I6ceec12aed297c57831a368a74d8b4e41f86f4c9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26624
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-03-30 21:47:20 +00:00
Adrian Herrera
e780202373 dev-arm: Adjust idreg value in RealViewCtrl
This is to match the FVP Foundation platform.
Priviledged software could query the SYS_ID register in the V2m
Motherboard controller to extract platform information:

https://
static.docs.arm.com/100961/1110/armv8_a_fp_ug_100961_1110_00_en.pdf

In particular:

* SYS_ID[31:28] (REV) = Revision Number
** Value = 0x3 -> FVP Foundation v9.6

* SYS_ID[27:16] (HBI) = Board Number
** Value = 0x010 -> FVP Foundation platform

* SYS_ID[15:12] (BLD) = Which variant of the GIC memory is implemented
in the model
** Value = 0x1 -> (!= legacy VE memory map)

* SYS_ID[11:8] (Arch) = Architecture
** Value = 0x1 -> Architectural model (FVP)

Change-Id: Ib9395eb872cb925c029077acfdd18e48478f779b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27184
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-03-30 17:12:04 +00:00
Giacomo Travaglini
4f6b8f1d71 dev-arm: Fix pci_mem_base setting in VExpress_GEM5_Base
This was not actually used and DTB was generated using an hardcoded
value.

Change-Id: Ie8fd63495df5cb56418593cf0dd5432dc2992eac
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27288
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2020-03-30 15:54:56 +00:00
Jordi Vaquero
ae69a12b3b arch-arm: ARMv8.3 CompNum, SIMD complex number support
This patch implements the CompNum SIMD instruction for armv8.3.
This instructions are Fcadd, Fcmla(vector and element) and
Vcadd, Vcmla ( vector and element).

+ isa/decoder/thumb.isa: Decoding changes for SIMD instructions in T32
+ isa/formats/fp.isa: Decoding changes for SIMD instructions in A32
+ isa/formats/uncond.isa: Decoding changes for SIMD instructions in A32
+ isa/formats/aarch64.isa: Decoding changes for SIMD instructions in A64
+ isa/formats/neon64.isa: Decoding changes for SIMD instructions in A64
+ isa/insts/neon.isa: Vcadd, Vcmla instruction implementation
+ isa/insts/neon64.isa: Fcadd, Fcmla instruction implementation
+ isa/templates/neon.isa: Modify templates for adding byElement support

Change-Id: I7f11ce88137dad077d2cad698dcaa9a79a3f317b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27183
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2020-03-30 11:13:27 +00:00
Gabe Black
f41abbdb5c scons: Enable LTO and partial linking with gcc >= 8.1.
The bug(s) which prevented LTO and partial linking from working with gcc
have been fixed in my local version (9.3), and according to one of the
original bug reports:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69866

A fix was committed in gcc version 8.1.

The original code left in the SConstruct describing the problem with
versions greated than 6.0 also enabled an -flinker-output option and set
it to "rel". That option doesn't show up in the gcc 8.4 documentation
even though it was added in 6.0, but in the 9.3 documentation it
describes it and says that it defaults to "rel" when the -r (partial
linking) option is used.

This *should* mean that LTO and partial linking can be used together
with no issues after version 8.1, and at most by version 9.3. If someone
finds that that isn't true, then the range of bad versions can be
expanded.

Change-Id: Ie0529d077a0042ef55e2af995d01430d1695c031
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27131
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
2020-03-28 00:12:19 +00:00
Gabe Black
1c59559ddb scons: Call summarize_warnings() when scons finishes building.
This will ensure that warnings are not all shoved off the end of the
scrollback buffer or lost in a sea of compiler lines, and that the user
will actually have a chance to see and read them.

Change-Id: I7129560482ebca903ec597f8b1cf8a9a84d98c9c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27130
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
2020-03-28 00:12:19 +00:00
Gabe Black
8b6fadd7d7 arm: Add a callSemihosting method that figures out the width.
Change-Id: Ic94987fffd04648932e5dd085ffeef8500e335cf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25951
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2020-03-27 23:52:37 +00:00
Gabe Black
19bba88354 arm: Add a gem5 specific pseudo op semihosting call.
This is in the range of call numbers set aside for extensions. When
called, it will extract the function to use from the first argument
slot. Then it calls the pseudoInst dispatching function using an ABI
which drops the return value (which is handled by semihosting itself)
and which extracts arguments from the remaining slots in the param
structure.

This makes gem5 pseudo ops available on CPU models which support
semihosting but not instruction based or address based "magic"
operations, aka hypercalls. This includes the fast model CPUs.

Change-Id: Ic4817f2b1e6aad7784af77a1a494cf614d4d4c6c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25950
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-03-27 21:33:03 +00:00
Gabe Black
f4697687ed riscv: Fix RISCV builds by updating its use of pseudoInst().
The signature of the function and RISCV's use of it changed
simultaneously, were independently verified, and then separately merged.
The combination of the two does not build successfully.

This change updates RISCV so it uses the new signature.

Change-Id: I6a944e664640c9086583d546870ed1fbfa84a3e7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27163
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nils Asmussen <nils.asmussen@barkhauseninstitut.org>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-03-27 21:14:51 +00:00
Gabe Black
3d572a49b8 scons: Add a mechanism to accumulate warnings to reprint at the end.
When building gem5, it's possible for warnings printed early in the
build to be quickly wisked away in a see of compile lines, never to be
seen again (or driven off the end of the scrollback buffer).

To avoid those messages getting lost or ignored, this change adds a
mechanism to aggregate them into a list so that they can be summarized
at the end of the build, successful or not.

Change-Id: Ie13320717698fcbcd3a8f8d1c062467e8d6d2914
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27129
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
2020-03-27 08:44:28 +00:00
Gabe Black
47579e693b scons: Use the textwrap module to wrap warnings/errors neatly.
Otherwise the error and warning messages get chopped off and wrapped by
the terminal wherever they happened to end. That's ugly and hard to
read.

This mechanism attempts to wrap the text using the console width which
it attempts to determine in two ways, first with shutil which should
work in python 3.3 and above, and then with the curses python module. If
neither of those works, it just falls back to 80 columns which is not
ideal but is reasonable.

Change-Id: I961936295505f93f5f36eb6d9cebc5073b5f793b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27128
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-03-27 08:44:28 +00:00
Gabe Black
ec236a55ee scons: Get rid of a redundant "Warning:" in the SConstruct.
The "warning()" method already prints "Warning:", so putting it in the
message itself means it gets printed twice.

Change-Id: Ic157355958fdf56739f865a926ecba071bb25c5e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27127
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-03-27 08:44:28 +00:00
Gabe Black
55ae5a886b scons: Replace find_first_prog() with the built in Detect().
The built in environment method Detect() does the same thing, that is it
finds the first program available from a list of options.

Change-Id: I3763ae5cc9dd22ee322908c0a7a2c037dc91d5a5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27126
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-03-27 08:44:28 +00:00
Gabe Black
b5a3c0de7e scons: Use the lsan-suppressions file when running internal commands.
These commands (like the marshal binary) might otherwise fail with
spurious leaks detected in the python library.

Change-Id: I042c2a811d465ac03f005672f328c0fb0b594494
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27125
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-03-27 08:44:28 +00:00
Gabe Black
c0e06b49af misc: Add Gabe Black as the scons and util maintainer.
Change-Id: I222c25ebd7b28ddad4bb903b6fd9e15b429b1039
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27143
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-03-27 08:41:14 +00:00
Hsuan Hsu
32b0eb0771 cpu-o3: Fix unset scoreboard in vector mode switching
This is another fix for the AArch32-AArch64 interprocessing issue
introduced in
3d15150d cpu, arch, arch-arm: Wire unused VecElem code in the O3 model.

Register mapping between AArch32 and AArch64 is explicitly defined in
ARMv8 manual. This allows software to read registers right after a state
switch without writing them first, and it is indeed common for software
to save registers to memory first before using them.

In gem5's implementation of vector mode switching, however, vectors may
not be marked as ready right after a state switch. Software reads toward
vectors at this time will stall O3CPU forever. This patch fixes this by
marking all mapped vectors (or vector elements, depending on AArch32 or
AArch64) as ready right after switching vector mode.

Change-Id: I609552c543dad8da66939c0a3079d73d48e92163
Signed-off-by: Hsuan Hsu <hsuan.hsu@mediatek.com>
Signed-off-by: Howard Wang <Howard.Wang@mediatek.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26203
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-03-27 08:01:33 +00:00
Hussein Elnawawy
d36f2fda12 mem-ruby: Checkpoint from MOESI_hammer Ruby hangs
Fix MOESI_hammer checkpoint hanging.
The function markRemoved() should be called before hitCallback(),
not after it. The reason is that hitCallback() checks if draining is
complete based on the value of "m_outstanding_count". And since
markRemoved() is responsible for decrementing "m_outstanding_count",
hitCallback() does not see that there are no outstanding requests.

Reported by: Timothy Hayes
Jira: https://gem5.atlassian.net/browse/GEM5-331
Change-Id: I14c34be79843b172ae994ab1792fe4ce6cf5cf6e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25683
Reviewed-by: Timothy Hayes <timothy.hayes@arm.com>
Reviewed-by: John Alsop <johnathan.alsop@amd.com>
Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-03-26 22:23:59 +00:00
Gabe Black
04365794b5 util: Add a file to suppress spurious lsan leaks in the python lib.
The python interpreter does some fancy things with memory which trips up
the lsan leak checker which comes along with asan. This file simply
tells lsan to ignore those leaks.

To use it when running a binary, set the LSAN_OPTIONS environment
variable to "suppressions=${PATH TO SUPPRESSIONS FILE}". To disable the
a report on the leaks that were suppressed, you should also set
"print_suppressions=0". Multiple options can be set by seperating them
with ":"s.

LSAN_OPTIONS=suppressions=util/lsan-suppressions:print_suppressions=0

Change-Id: Ie4d712c6b95f429e67361c41a9b545a8536f2511
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27124
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-03-26 21:44:44 +00:00
Gabe Black
bb3bc1fdd0 scons: Use the scons environment when marshalling.
scons maintains an environment (in the shell sense) in the ENV
construction variable for use when running external programs. When we
run the "marshal" program which gathers up python objects to embed in
the gem5 binary, it's run by subprocess instead of through scons, and it
uses its own environment inherited from the host system.

Instead, this change makes the subprocess function use the scons
environment when calling "marshal". This ensures the environment is
consistent between this command and other commands scons runs.

This is usually not very important, but some tools like asan take
options set through the environment, and they may need to be adjusted
sometimes.

Change-Id: I671b447657ed8fad45fac7393cc1c09073bf3d3a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27123
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-03-26 21:44:36 +00:00
Bobby R. Bruce
aeb4b53801 tests,misc: Updated presubmit YAML to use main.py '-t' flag
This minor change reduces the presubmit build time by about 10 to 15
minutes.

Change-Id: I3a87d1a720b17fd22a9dbdbeebfb32e4be178c56
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27064
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-03-26 18:13:57 +00:00
Bobby R. Bruce
0ea4313255 tests: Migrated 10.linux-boot scons-based test to testlib
This test has purposely been designed to be easily extendible for future
x86 boot tests. Right now, it only runs two basic Ubuntu boot test
setups.

Change-Id: I81385b5dfc0764af2ec02999eb26e523bd09a595
Issue-on: https://gem5.atlassian.net/browse/GEM5-109
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26324
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-03-26 18:13:34 +00:00
Giacomo Travaglini
95e6767601 dev-arm: Don't use args and kwargs on attachIO
This is matching the attachOnChipIO style, and fixing the error of the
dma_ports kwarg being forwarded to the _attach_mem

Change-Id: Ib3ecf2fc18c488d938bbbf63eab3d7693cdb7d06
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27086
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
2020-03-26 16:08:51 +00:00
Gabe Black
5ae5fa85d7 arm: Return whether a semihosting call was recognized/handled.
Otherwise there's no way to determine whether the return value was from
the semihosting mechanism itself, or from one of the calls. There would
also be no way to determine whether a call had actually happened.

Change-Id: Ie2da812172fe2f9c1e2b5be95561863bd12920b1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25949
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
2020-03-26 09:00:05 +00:00
Nils Asmussen
25a538ff20 arch-riscv: print information about faults.
Change-Id: Ic69b788d508bab1044b693860c7d942963bed3f9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25646
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-03-26 08:28:43 +00:00
Nils Asmussen
6362e8b2d2 arch-riscv: added support for pseudo instructions.
Change-Id: I4f73f8fcf62def8815e82555fc2a67f89efc09d1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25645
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
2020-03-26 08:28:43 +00:00
Gabe Black
268c9d836f arch,sim: Return whether or not a pseudo inst was recognized.
Otherwise there's no way to distinguish whether return values are from
the calls themselves, including what they mean in the context (success
or failure?) or the pseudo inst dispatch function itself.

Change-Id: I3e71c277f175c69af0d1adeb3299d88d095dfa84
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25948
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
2020-03-26 06:19:17 +00:00
Matthew Poremba
209c0663d5 sim-se: Add special paths for MPI, libnuma, ROCm support
Add new pseudo files which are read by various runtime libraries
including MPI, libnuma, and ROCm. New paths include /proc/self/maps,
/dev/urandom, and /sys/devices/system/cpu/online.

Change-Id: I00a82788cff9d6f4f16fc56230b18be9b76c4015
Signed-off-by: Brandon Potter <Brandon.Potter@amd.com>
Signed-off-by: Michael LeBeane <Michael.Lebeane@amd.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25367
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2020-03-25 21:55:21 +00:00
Gabe Black
20189987ef arm: Optionally enable gem5 extended semihosting calls.
ARM's semihosting interface defines call numbers up to 0xff to be
for standardized use, and says that custom calls should go above this
number.

This new mechanism will let the caller decide whether it wants to
enable these extended calls, or if they should be ignored and only
standard calls should be recognized.

Change-Id: I34b01a4439c8a88242971ac486e34d810b054baf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25947
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-03-25 21:09:41 +00:00
Matthew Poremba
8824f25da4 sim-se: Update mmap, munmap, mremap to use MemState
This updates the syscalls for mmap, munmap, and mremap. The mmap
changes now create a virtual memory area through the MemState class
to allow for lazy allocation of mmapped regions. This provides
substantial performance boost for sparse usage of mmaps. The munmap
syscall is added to reclaim the virtual memory area reserved for the
mmapped region. The mremap syscall moves or resizes an mmapped region
and updates the corresponding virtual memory area region to keep the
page tables in sync.

Change-Id: Ide158e69cdff19bc81157e3e9826bcabc2a51140
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26863
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-03-25 19:18:15 +00:00
Matthew Poremba
5c2fb0c652 sim-se: Switch to new MemState API
Switch over to the new MemState API by specifying memory regions for
stack in each ISA, changing brkFunc to use MemState for heap memory,
and calling the MemState fixup in fixupStackFault (renamed to just
fixupFault).

Change-Id: Ie3559a68ce476daedf1a3f28b168a8fbc7face5e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25366
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-03-25 19:18:15 +00:00
Matthew Poremba
56ee199b3d sim-se: Extend MemState API to use VMAs
Extend the MemState API to handle tracking dynamically sized memory
regions of a Process class which may be added, moved, removed, or
change in size during the course of simulation. This utilizes the
virtual memory areas (VMA) class to track individual regions and
provides a fixup method to handle physical page allocation in case of
a page fault. This allows for lazy allocation of the stack, heap, and
mmap regions of memory.

Change-Id: I3ef10657e5f8e8f0e328bdf0aa15a27b1dde39bf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25483
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-03-25 15:42:45 +00:00
Giacomo Travaglini
bf38808666 configs: Use ArmFsWorkload for Arm baremetal
Change-Id: Ie6bfdd9b30438bc6eaf22bc79dcc1690ffa039be
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26991
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-03-25 14:43:31 +00:00
Adrian Herrera
700bf943f3 cpu: IntrControl, clear all and check helpers
This patch extends the IntrControl to provided additional member
functions for (1) clearing all pending interrupts in a PE and (2)
checking for any pending interrupt in a PE. These are intended to
be used from interrupt management related peripherals.

Change-Id: I06b553872ed469e7449b872a0716865773ace154
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26809
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-03-25 09:49:20 +00:00