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arm: Optionally enable gem5 extended semihosting calls.

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ARM's semihosting interface defines call numbers up to 0xff to be
for standardized use, and says that custom calls should go above this
number.

This new mechanism will let the caller decide whether it wants to
enable these extended calls, or if they should be ignored and only
standard calls should be recognized.

Change-Id: I34b01a4439c8a88242971ac486e34d810b054baf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25947
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2020-02-26 04:59:25 -08:00
parent 8824f25da4
commit 20189987ef
4 changed files with 20 additions and 10 deletions
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14
src/arch/arm/semihosting.cc
View File

@@ -154,9 +154,14 @@ ArmSemihosting::ArmSemihosting(const ArmSemihostingParams *p)
}
void
ArmSemihosting::call64(ThreadContext *tc)
ArmSemihosting::call64(ThreadContext *tc, bool gem5_ops)
{
RegVal op = tc->readIntReg(ArmISA::INTREG_X0 & mask(32));
if (op > MaxStandardOp && !gem5_ops) {
unrecognizedCall<Abi64>(
tc, "Gem5 semihosting op (0x%x) disabled from here.", op);
return;
}
auto it = calls.find(op);
if (it == calls.end()) {
@@ -173,9 +178,14 @@ ArmSemihosting::call64(ThreadContext *tc)
}
void
ArmSemihosting::call32(ThreadContext *tc)
ArmSemihosting::call32(ThreadContext *tc, bool gem5_ops)
{
RegVal op = tc->readIntReg(ArmISA::INTREG_R0);
if (op > MaxStandardOp && !gem5_ops) {
unrecognizedCall<Abi32>(
tc, "Gem5 semihosting op (0x%x) disabled from here.", op);
return;
}
auto it = calls.find(op);
if (it == calls.end()) {

4
src/arch/arm/semihosting.hh
View File

@@ -214,9 +214,9 @@ class ArmSemihosting : public SimObject
ArmSemihosting(const ArmSemihostingParams *p);
/** Perform an Arm Semihosting call from aarch64 code. */
void call64(ThreadContext *tc);
void call64(ThreadContext *tc, bool gem5_ops);
/** Perform an Arm Semihosting call from aarch32 code. */
void call32(ThreadContext *tc);
void call32(ThreadContext *tc, bool gem5_ops);
public: // SimObject and related interfaces
void serialize(CheckpointOut &cp) const override;

8
src/arch/arm/system.cc
View File

@@ -180,15 +180,15 @@ ArmSystem::haveSemihosting(ThreadContext *tc)
}
void
ArmSystem::callSemihosting64(ThreadContext *tc)
ArmSystem::callSemihosting64(ThreadContext *tc, bool gem5_ops)
{
getArmSystem(tc)->semihosting->call64(tc);
getArmSystem(tc)->semihosting->call64(tc, gem5_ops);
}
void
ArmSystem::callSemihosting32(ThreadContext *tc)
ArmSystem::callSemihosting32(ThreadContext *tc, bool gem5_ops)
{
getArmSystem(tc)->semihosting->call32(tc);
getArmSystem(tc)->semihosting->call32(tc, gem5_ops);
}
void

4
src/arch/arm/system.hh
View File

@@ -314,10 +314,10 @@ class ArmSystem : public System
static bool haveSemihosting(ThreadContext *tc);
/** Make a Semihosting call from aarch64 */
static void callSemihosting64(ThreadContext *tc);
static void callSemihosting64(ThreadContext *tc, bool gem5_ops=false);
/** Make a Semihosting call from aarch32 */
static void callSemihosting32(ThreadContext *tc);
static void callSemihosting32(ThreadContext *tc, bool gem5_ops=false);
/** Make a call to notify the power controller of STANDBYWFI assertion */
static void callSetStandByWfi(ThreadContext *tc);