Commit Graph

14257 Commits

Author SHA1 Message Date
Bobby R. Bruce
7601fcfba6 cpu-minor: Check pc valid before printing (#107)
In https://gem5-review.googlesource.com/c/public/gem5/+/52047 inst.pc
was changed from an object to a pointer. It is possible that this
pointer is null (e.g., if there is an interrupt and there is a bubble).
Make sure to check that it's not null before printing.

I believe that other places this pointer is dereferenced without an
explicit null check are safe, but I'm not certain.

Should fix #97 

Change-Id: Idbe246cfdb62d4d75416d41b451fb3c076233bbc
2023-07-25 17:14:38 -07:00
Melissa Jost
556c9154dd base: Add maybe_unused to findLsbSetFallback (#109)
When compiling with clang-14 I received the following error:

```
src/base/bitfield.hh:328:1: error: function 'findLsbSetFallback' is not needed and will not be emitted [-Werror,-Wunneeded-internal-declaration]
```

This function was introduced in PR #76.
This fixes this compiler warning/error by using `[[maybe_unused]]`.

Change-Id: I0b99eab0a9e42ee1687e7a0594a5a7bf9588b422
2023-07-25 10:41:59 -07:00
Bobby R. Bruce
78849ac4fb Merge branch 'develop' into fix-bitfield-unused 2023-07-24 11:05:05 -07:00
Giacomo Travaglini
7dba30209a arch-arm: Hook TLBIOS instructions to the TlbiShareable obj
FEAT_TLBIOS has been introduced by a recent patch [1] which
was however missing to include the outer shareable case in the
Msr disambiguation switch. Which meant the TLBIOS instructions
were decoded as normal MSR instructions, with no effect whatsoever
on the TLBs

[1]: https://gem5-review.googlesource.com/c/public/gem5/+/70567

Change-Id: I41665a4634fbe0ee8cc30dbc5d88d63103082ae9
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2023-07-24 09:05:01 +01:00
Daniel Kouchekinia
984499329d mem-ruby,configs: Add GLC Atomic Latency VIPER Parameter (#110)
Added a GLC atomic latency parameter (glc-atomic-latency) used when
enqueueing response messages regarding atomics directly performed in
the TCC. This latency is added in addition to the L2 response latency
(TCC_latency). This represents the latency of performing an atomic
within the L2.

With this change, the TCC response queue will receive enqueues with
varying latencies as GLC atomic responses will have this added GLC
atomic latency while data responses will not. To accommodate this in
light of the queue having strict FIFO ordering (which would be violated
here), this change also adds an optional parameter bypassStrictFIFO to
the SLICC enqueue function which allows overriding strict FIFO
requirements for individual messages on a case-by-case basis. This
parameter is only being used in the TCC's atomic response enqueue call.

Change-Id: Iabd52cbd2c0cc385c1fb3fe7bcd0cc64bdb40aac
2023-07-23 15:57:06 -05:00
Gabriel Busnot
75b6fa5ad1 base: Ostream helpers (iterable, tuple, pair, enum, pointers, optional) (#77)
* base: Enable stl_helpers::operator<< in _formatString

The string format (%s) eventually relies on bare operator<< to
display any type T. This gives the opportunity to use the helpers in
stl_helpers. This patch enables printing enums, pairs, tuples,
vectors, maps and others in a PRINTF debug macro without any extra
manual operation.

Change-Id: I8ac85133ebadcb95354598c1cfe687d8fffb89e2

* base: Add Printer util class to force use of operator<< helpers

Wrapping any value in a Printer instance before using operator<< will
force the use of stl_helpers::operator<<.

Change-Id: I7b505194eeabc3e0721effd9b5ce98f9e151b807

* base: Fix typo in ostream_helpers.hh

Change-Id: I283a5414f3add4f18649b77153dcbcc8661bc81e

* base: Disambiguate null optional representation in ostream helper

Change-Id: I5b093555688566cc405248d3a448a8f3efa67888

* base: Add unit test for std::optional ostream helper

Change-Id: I6fb9ced5e6461de5685638a162b5534e10710e20

* base: Ostream helpers Printer unit test

Change-Id: I11db89e85fd40c12bceecb41cadee78b8e871d7b

* base: Unit test for ostream helpers for pointers and smart ptr

Change-Id: Ifa87e8b69fdd9a4869250ab40311f352e8f54ed9

* base: Coding style fix in ostream_helpers.test.cc

Change-Id: I095c7048fad35e63f979aa601bfc8cde65c9077b

* base: Test shared_ptr in ostream_helpers.test.cc

Change-Id: I553df0614f1dd6eef2061c4dc1794af8c543b78f

---------

Co-authored-by: Gabriel Busnot <gabriel.busnot@arteris.com>
2023-07-21 11:11:09 -07:00
Jason Lowe-Power
27cfe4cc1b Merge branch 'develop' into fix-invalid-pc-on-bubble 2023-07-21 08:10:03 -07:00
Bobby R. Bruce
01623fac68 stdlib,configs,tests: Remove deprecated Resource classes usage (#102)
* stdlib,configs,tests: Remove `Resource` class use

This class is deprecated, but was still used in various example
configuration scriots and tests. This patch replaces it with the
`obtain_resource` function.

Change-Id: I0c89bf17783ccaaafc18072aaeefb5d1e207bc55

* configs: Remove `CustomDiskImageResource` use

The class is deprecated but was still used in the SPEC example scripts.
This patch replaces it with the `DiskImageResource` class.

Change-Id: Ie0697fe59a3d737b05eb45ff3bc964f42b0387e0

* configs,tests: Remove `CustomResource` use

This class is deprecated but was still used in example scripts and
mentioned, incorrectly, in comments in the pyunit tests. This patch
removes these.

Change-Id: Icb6d02f47a5b72cd58551e5dcd59cc72d6a91a01

* stdlib: Remove '\' in Workload docstring example

This example shows how to use the Workload. The backslash is not correct Python and would fail if used in this way.

Co-authored-by: Jason Lowe-Power <jason@lowepower.com>

---------

Co-authored-by: Jason Lowe-Power <jason@lowepower.com>
2023-07-20 23:08:39 -07:00
Bobby R. Bruce
573573b5ba base: Add maybe_unused to findLsbSetFallback
When compiling with clang-14 I received the following error:

```
src/base/bitfield.hh:328:1: error: function 'findLsbSetFallback' is not needed and will not be emitted [-Werror,-Wunneeded-internal-declaration]
```

This function was introduced in PR #76.
This fixes this compiler warning/error by using `[[maybe_unused]]`.

Change-Id: I0b99eab0a9e42ee1687e7a0594a5a7bf9588b422
2023-07-20 15:04:06 -07:00
Adwaith R Krishna
427b4d596e mem-garnet: Fix packet_id val in flit (#72)
Change-Id: I163b5a32972783bf2e99f3383b9f86776577b727

Co-authored-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2023-07-20 13:56:31 -07:00
Jason Lowe-Power
29832849f7 cpu-minor: Check pc valid before printing
In https://gem5-review.googlesource.com/c/public/gem5/+/52047 inst.pc
was changed from an object to a pointer. It is possible that this
pointer is null (e.g., if there is an interrupt and there is a bubble).
Make sure to check that it's not null before printing.

I believe that other places this pointer is dereferenced without an
explicit null check are safe, but I'm not certain.

Change-Id: Idbe246cfdb62d4d75416d41b451fb3c076233bbc
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
2023-07-20 13:23:16 -07:00
Kunal Pai
3c6563d6f7 stdlib: Change resource compatibility warning (#91)
* stdlib: Change resource compatibility warning

If the gem5 version is "develop", the warning will not
be thrown.

Change-Id: Id2be1c4323c6ca06c5503c2885c1608f8d119420

* stdlib: Change resource compatibility warning

If the gem5 version is "develop", the warning will not
be thrown.

Change-Id: Id2be1c4323c6ca06c5503c2885c1608f8d119420

* tests: Edit obtain_resources warning test

Since we are editing the warning message for
the develop branch, the test removes the
warning message as well.

Change-Id: I90882340188360bb3435344cdc14b324412c6c0e

---------

Co-authored-by: Jason Lowe-Power <jason@lowepower.com>
2023-07-20 12:00:49 -07:00
Hoa Nguyen
f7da973f34 cpu-kvm: Make using perf when using KVM CPU optional (#95)
* cpu-kvm: Add a variable signifying whether we are using perf

Change-Id: Iaa081e364f85c863f781723b5524d267724ed0e4
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>

* cpu-kvm: Making it clear the functionalities are specific to KVM

Change-Id: I982426f294d90655227dc15337bf73c42a260ded
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>

* cpu-kvm: Make perf optional

Change-Id: I8973c2a96575383976cea7ca3fda478f83e95c3f
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>

* configs: Add an example config of using KVM without perf

Change-Id: Ic69fa7dac4f1a2c8fe23712b0fa77b5b22c5f2df
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>

* Apply suggestions from code review

Co-authored-by: Jason Lowe-Power <jason@lowepower.com>

* misc: Add an example to the panic

Change-Id: Ic1fdfb955e5d8b9ad1d4f0a2bf30fa8050deba70
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>

* misc: Add warning of not using perf when using KVM CPU

Change-Id: I96c0832fb48c63a79773665ca6228da778ef0497
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>

* misc: Fix stuff

Change-Id: Ib407ae7407955b695f0e0f2718324f41bb0d768f
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>

* misc: style fix

Change-Id: I7275942e43f46140fdd52c975f76abb3c81b8b0a
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>

---------

Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Co-authored-by: Jason Lowe-Power <jason@lowepower.com>
2023-07-20 10:34:44 -07:00
Daniel Kouchekinia
1705853b12 mem-ruby: Added support for non-system-scope atomics in VIPER (#101)
Added support for performing non-SLC-set atomics in the TCC.
Previously, all atomics were being passed on by the TCC to the
directory. With this change, atomics will only be passed on if the SLC
bit is set or if the line isn't present or available in the TCC.

If a non-SLC atomic is passed on to the directory because it is not
present in the TCC, the atomic will be performed on the return path on
the Data event. To accommodate the directory not performing the atomic
in this case, this change also passes the SLC bit on to the directory.

The previously-named "Atomic" action has been renamed to
"AtomicPassOn", with the new "Atomic" corresponding to an atomic
performed directly in the TCC.

Change-Id: Ibf92f71ddceb38bd1b0da70b0a786cc4c3cf2669
2023-07-20 11:48:08 -05:00
rogerchang23424
566308dad9 scons: Add extra parent dir to CPPPATH if --no-duplicate-sources (#104)
In the previous version of gem5, the source files of extra directories
will copy to build directory for compilation. It will not be a problem
if the extra directories include *.h(*.hh) from the other extra
directories.

After the patch applied from the change
(https://gem5-review.googlesource.com/c/public/gem5/+/68758). The
source files of extra directories will not copy to the build directory
unless the user compiles gem5 with "--duplicate-sources". It will
cause the compilation error if the code includes a header file from
other repositories.

For example, assume we want to compile gem5 with "foo/bar1" and
"foo/bar2" repositories and they are gem5-independent. There are some
header files in "foo/bar1/a.h" "foo/bar1/b.h" and "foo/bar2/d.h". If
the code "foo/bar1/sample.c" tries to include the file "foo/bar2/d.h".
They usually include the file by declare "#include bar2/d.h" in
foo/bar1/sample.c. It can work if --duplicate-sources is specified in
gem5 build because they will copy to <builddir>/bar1 and
<builddir>/bar2 respectively, and -I<builddir> is specified by default
whether duplicate_sources or not. It will raise the compilation error
if the user does not specify it.

The change is aimed to let the situation work without
duplicate-sources specified by adding parent extra directory, and
adding them before the extra directories. If the --duplicate-sources
specified, it will not add parent extra directories to avoid repeat
include paths.

Change-Id: I461e1dcb8266d785f1f38eeff77f9d515d47c03d
2023-07-20 09:35:45 -07:00
rogerchang23424
5d2edca1e3 arch-riscv: Set default check alignment True (#98)
Raise misaligned trap if effective address if not aligned by default

Change-Id: I634aa7ddbf5282fc583316fc77ab1e37bfe415e3
2023-07-19 11:14:27 -07:00
Gabriel Busnot
4c4419296b base: Unit tests miscellaneous patches (#73)
* base: Fix Memoizer constructor parameter type

* base: switch from new to mk_unq in amo.test.cc

* base: Fix memory management in IniFile

* base: Fix memory management in Trie

* sim: Fix out-of-bounds access in CheckpointIn::setDir

Change-Id: Iac50bbf01b6d7acc458c786da8ac371582a4ce09

---------

Co-authored-by: Gabriel Busnot <gabriel.busnot@arteris.com>
2023-07-19 08:45:29 -07:00
Daniel Kouchekinia
4d9bd7dedf base: Added missing backup dummy __has_builtin definition (#99)
Added dummy definition of __has_builtin to bitfield.hh's hasBuiltinCtz,
which is already being done in popCount.

Change-Id: I4a1760a142209462bb807c6df4bc868284b6f5f3
2023-07-19 02:07:39 -07:00
Lingkang
573523c07a python: fix fatal in main.py (github #78) (#93)
* python: fix fatal in main.py (github #78)

Issue-On: https://github.com/gem5/gem5/issues/78

* python: fix fatal in main.py (github #78)

Issue-On: https://github.com/gem5/gem5/issues/78
Change-Id: I80855b05168a067ddd7706ad9fd7e71e75bfd3b1

---------

Co-authored-by: Jason Lowe-Power <jason@lowepower.com>
2023-07-18 14:00:57 -07:00
Gabriel Busnot
6fb72d84e1 base: Find lsb set generalization and optimization (#76)
* base: Generalize findLsbSet to std::bitset<N>

* base: Split builtin and fallback implementations of findLsbSet

* base: Add more unit testing for findLsbSet

Change-Id: Id75dfb7d306c9a8228fa893798b1b867137465a9

---------

Co-authored-by: Gabriel Busnot <gabriel.busnot@arteris.com>
2023-07-17 15:32:04 -07:00
Bobby R. Bruce
f80015ea18 misc: Update README/README.md (#71)
* misc: Update README to README.md

This change converts the text-based README to markdown. This works
better with modern source-control systems, most notably, GitHub.

The README.md has been broken down into sections to better organize the
document.
This section now included expanded information on Reporting bugs and
Requesting Features.

Due to renaming 'README' to 'README.md', this code was generating the
following for "info.py":

```
README.md = "<FILE CONTENTS HERE>"
```

As '.' is used to access member variables/methods in python. To fix this
"infopy.oy" now replaces "." with "_". As such the generated in in
"info.py" is now:

```
README_MD = "<FILE CONTENTS HERE>"

This puts GitHub Discussions and GitHub Issues towards the top of the
list. This is to incentivize their usage.

Change-Id: I18018ba23493f43861544497f23ec59f1e8debe1

---------

Co-authored-by: Jason Lowe-Power <jason@lowepower.com>
2023-07-17 15:30:35 -07:00
wmin0
162f2e2dba scons: Use pkgconfig to get correct Protobuf dependency (#68)
Latest protobuf library depends on abseil libraries. We should rely on
pkgconfig to give us correct dependency. We still keep the old check as
fallback.

Change-Id: I529ea1f61e5bbc16b2520ab1badff3d8264f1c33
2023-07-17 15:29:05 -07:00
KaiBatley
efa1d87add configs: fix GPU's default number of HW barrier/CU (#92)
AMD GCN3 and Vega GPUs assume a max of 16 WG/CU.  Any GPU WG with more
than 1 WF requires a hardware barrier to allow WFs in the WG to
synchronize locally.  However, currently the default gem5 GPU
configuration assumes only 4 barriers per CU, which artificially
prevents applications with > 4 WG/CU that could run simultaneously
from running simultaneously.

This fix resolves this by updating the default number of hardware barriers
per CU to 16, which mimics the support described in slide 39 here:
https://www.olcf.ornl.gov/wp-content/uploads/2019/10/
ORNL_Application_Readiness_Workshop-AMD_GPU_Basics.pdf

Change-Id: Ib7636a13359d998e676c1790f436a83ce88cbfc0
2023-07-17 10:42:40 -07:00
Jason Lowe-Power
442923c414 Add feature to output citations automatically based on configuration (#90)
This change adds a new file to m5out which is citations.bib.
This file will contain the citations to the papers which describe the
aspects of the gem5 simulator that the simulation uses. In other words,
each simulation configuration could generate a different bib file
referencing different works.

Each SimObject can now have a set of citations associated with it. After
the system is built (in `instantiate`), the citations.bib file is
created by parsing all SimObjects that have been instantiated and taking
the union of their associated citations.

This commit is not meant to add all citations, but to act as an example
for others to add more citations to gem5.

Change-Id: Icd5c46fd9ee44adbeec1fea162657f5716f7e5ef
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
2023-07-17 10:41:51 -07:00
Daniel Kouchekinia
f8f5dd98bf mem-ruby: Added WIB State to VIPER TCC Cache (#67)
Added WIB (Waiting on Writethrough Ack; Will be Bypassed) state which
is transitioned to when a dirty line in the TCC is evicted in a
bypassed read. Previously, we were transitioning to invalid.

While a WI (Waiting on Writethrough Ack) state exists, transitions from
it on WBAck deallocates the TBE, which contains SLC bit information
needed to trigger the Bypass event when the read response from the
directory comes in.

Without this change, WB acknowledgements from the directory in read
bypass evicts (with the SLC bit set) were being treated as if they were
read responses, leading to an invalid transition panic.

Change-Id: I703c3fe8af0366856552bb677810cb1a8f2896de
2023-07-17 10:17:47 -07:00
rogerchang23424
52d9259396 arch-riscv: Fix clearLoadReservation merge (#81)
The previous change
(https://gem5-review.googlesource.com/c/public/gem5/+/71818) makes
the clearLoadReservation be RISC-V only.

Change-Id: I5df1a7fa688489d57fff8da937e3c8addfe4c299
2023-07-14 08:48:43 -07:00
Mahyar Samani
b2fcc558d8 stdlib: Deviding range for linear multicore. (#63)
This patch changes the way memory ranges are devided when using
multiple cores for linear traffic. The current state assigns the
same range to multiple linear generators so all the cores start
generating the same trace. This patch devides the overall range
assigned to the generator ([min_addr:max_addr]) between the cores.

Change-Id: I49f69b3d61b590899f8d54ee3be997ad22d7fa9b

Co-authored-by: Jason Lowe-Power <jason@lowepower.com>
Co-authored-by: mkjost0 <50555529+mkjost0@users.noreply.github.com>
Co-authored-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2023-07-14 07:33:21 -07:00
Giacomo Travaglini
18470b4747 arch-arm: Fix assert fail when UQRSHL shiftAmt==0 (#75)
When shiftAmt is 0 for a UQRSHL instruction, the code called bits() with
incorrect arguments. This fixes a left-shift of 0 to be a NOP/mov, as
required.

Change-Id: Ic86ca40ac42bfb767a09e8c65a53cec56382a008

Co-authored-by: Marton Erdos <marton.erdos@arm.com>
2023-07-13 10:57:51 -07:00
Bobby R. Bruce
753933d471 gpu-compute, tests: Fix GPU_X86 compilation, add compiler tests (#64)
* gpu-compute: Remove use of 'std::random_shuffle'

This was deprecated in C++14 and removed in C++17. This has been
replaced with std::random. This has been implemented to ensure
reproducible results despite (pseudo)random behavior.

Change-Id: Idd52bc997547c7f8c1be88f6130adff8a37b4116

* dev-amdgpu: Add missing 'overrides'

This causes warnings/errors in some compilers.

Change-Id: I36a3548943c030d2578c2f581c8985c12eaeb0ae

* dev: Fix Linux specific includes to be portable

This allows for compilation in non-linux systems (e.g., Mac OS).

Change-Id: Ib6c9406baf42db8caaad335ebc670c1905584ea2

* tests: Add 'VEGA_X86' build target to compiler-tests.sh

Change-Id: Icbf1d60a096b1791a4718a7edf17466f854b6ae5

* tests: Add 'GCN3_X86' build target to compiler-tests.sh

Change-Id: Ie7c9c20bb090f8688e48c8619667312196a7c123
2023-07-11 14:35:03 -07:00
Gabriel Busnot
73afee1e0d base: Provide stl_helpers::operator<< for more types
This operator can be safely brought in scope when needed with "using
stl_helpers::operator<<".

In order to provide a specialization for operator<< with
stl_helpers-enabled types without loosing the hability to use it with
other types, a dual-dispatch mechanism is used. The only entry point
in the system is through a primary dispatch function that won't
resolve for non-helped types. Then, recursive calls go through the
secondary dispatch interface that sort between helped and non-helped
types. Helped typed will enter the system back through the primary
dispatch interface while other types will look for operator<< through
regular lookup, especially ADL.

Change-Id: I1609dd6e85e25764f393458d736ec228e025da32
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67666
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
2023-07-10 23:00:45 +00:00
Luming Wang
c634b23305 sim,python: follow the new CPython startup sequence
Currently, gem5 suffers from several bugs related
to Python interpreter's locale encoding issues.
gem5 will crash when the working directory contains
Non-ASCII characters.

The reason is that Python 3.8+ introduces a new
interpreter startup sequence [1]. The startup
sequence consists of three phases:

1. Python core runtime preinitialization
2. Python core runtime initialization
3. Main interpreter configuration

Stage 1 determining the encodings used for system
interfaces.

However, gem5 doesn't preinitialize the Python
interpreter. Thus, the locale settings do not take
effect. This patch preinitialize the Python for
Python 3.8+.

Also, this patch avoid the use of `Py_SetProgramName`,
which is deprecated since Python 3.11[3].

[1] https://peps.python.org/pep-0432/
[2] https://peps.python.org/pep-0587/
[3] https://docs.python.org/3/c-api/init.html#c.Py_SetProgramName

Change-Id: I08a2ec6ab2b39a95ab194909932c8fc578c745ce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70898
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Roger Chang <rogerycchang@google.com>
2023-07-10 23:00:31 +00:00
Yang Liu
35763bdfb2 arch: Add setRegOperand in VecRegOperand
VecRegOperand also need setRegOperand method to write back execution
result.

Change-Id: Ie50606014827c14a7219558dd003eb4747231649
Co-authored-by: Xuan Hu <huxuan@bosc.ac.cn>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67292
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-07-10 22:59:12 +00:00
Bobby R. Bruce
a43f8e6904 stdlib: Allow passing of func list as exit_event generator
Allows for a passing of functions to specify actions to execute on an
exit event via the Simulator module in the stdlib.

The list of functions must have no manditory arguments and return True
if the Simulation is to exit upon the function call's completion.

Issue-on: https://gem5.atlassian.net/browse/GEM5-1126
Change-Id: Ia88caf2975227e78243763627acab9e9f89e2a7d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62691
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-07-10 22:56:54 +00:00
Bobby R. Bruce
63bdde4f63 arch-riscv: Remove clearLoadReservation
This was added due to a bad merge from stable to develop.

Change-Id: I7adf9604ee4d6f1cf11c404af5e8e1c071461a4a
2023-07-10 15:28:41 -07:00
Bobby R. Bruce
160681cabf misc: Update version info for develop branch
Change-Id: Iecee9e230c1c80f5675ec14bbeba9f7d9e2b8664
2023-07-10 12:28:44 -07:00
Bobby R. Bruce
54501c3e2b misc: Merge branch 'stable' into 'develop'
This ensures all commits in v23.0 are now in the develop branch.

Change-Id: I791346115dd123f3541a3c8060482e00cf4dbfb5
2023-07-10 12:24:27 -07:00
Bobby R. Bruce
20ee3b9762 stdlib: Remove simulator.py beta warnings
This component is no longer in a beta state

Change-Id: I8e309771aaa03197cf1738ad0af57c253ad58ecd
2023-07-07 18:21:44 -07:00
Bobby R. Bruce
e377e15c07 misc: Update gem5 version to v23.0.0.0
Change-Id: Ie14b35a62a152e3d78b16bcd4c92ec9a790f1396
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71724
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
2023-07-08 00:31:31 +00:00
Matthew Poremba
387fc6964e gpu-compute,configs: Make sim exits conditional
The unconditional exit event when a kernel completes that was added in
c644eae2dd is causing scripts that do not
ignore unknown exit events to end simulation prematurely. One such
script is the apu_se.py script used in SE mode GPU simulation. Make this
exit conditional to the parameter being set to a valid value to avoid
this problem.

Change-Id: I1d2c082291fdbcf27390913ffdffb963ec8080dd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/72098
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
(cherry picked from commit 3756af8ed9)
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/72138
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
2023-07-07 21:22:45 +00:00
Matthew Poremba
578eaead47 dev-amdgpu: Perform frame writes atomically
The PCI read/write functions are atomic functions in gem5, meaning they
expect a response with a latency value on the same simulation Tick. For
reads to a PCI device, the response must also include a data value read
from the device.

The AMDGPU device has a PCI BAR which mirrors the frame buffer memory.
Currently reads are done atomically, but writes are sent to a DMA device
without waiting for a write completion ACK. As a result, it is possible
that writes can be queued in the DMA device long enough that another
read for a queued address arrives. This happens very deterministically
with the AtomicSimpleCPU and causes GPUFS to break with that CPU.

This change makes writes to the frame BAR atomic the same as reads. This
avoids that problem and as a result the AtomicSimpleCPU can now load the
driver for GPUFS simulations.

Change-Id: I9a8e8b172712c78b667ebcec81a0c5d0060234db
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71898
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matthew Poremba <matthew.poremba@amd.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
(cherry picked from commit 079fc47dc2)
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/72079
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
2023-07-07 21:22:30 +00:00
Bobby R. Bruce
04b4a4705a stdlib: Change default gem5-resources DB collection
This was set to "test_collection", which was used during development.
Changing to "resources".

Change-Id: I52c83c6b73f3a227fbb05dc321a4bc38210ad71c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/72158
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
2023-07-07 19:51:59 +00:00
Bobby R. Bruce
4912e90978 stdlib: Change default gem5-resources DB collection
This was set to "test_collection", which was used during development.
Changing to "resources".

Change-Id: I52c83c6b73f3a227fbb05dc321a4bc38210ad71c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/72018
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-07-07 15:52:52 +00:00
Matthew Poremba
3756af8ed9 gpu-compute,configs: Make sim exits conditional
The unconditional exit event when a kernel completes that was added in
c644eae2dd is causing scripts that do not
ignore unknown exit events to end simulation prematurely. One such
script is the apu_se.py script used in SE mode GPU simulation. Make this
exit conditional to the parameter being set to a valid value to avoid
this problem.

Change-Id: I1d2c082291fdbcf27390913ffdffb963ec8080dd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/72098
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-07-07 14:12:54 +00:00
Gabriel Busnot
b8af5f6a6c base: stl_hlp::unordered_{map,set} with stl_hlp::hash by default
Change-Id: Iad01d7fa6ff6293a2d931ba796666ad3550c6e44
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67664
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
2023-07-07 10:17:54 +00:00
Gabriel Busnot
eb241e8a99 base: Provide several hash implementations for common types
These types include std::pair, std::tuple, all iterable types and any
composition of these. Convenience hash factory and computation
functions are also provided.

These functions are in the stl_helpers namespace and must not move to
::std which could cause undefined behaviour. This is because
specialization of std templates for std or native types (or
composition of these) is undefined behaviour. This inconvenience can't
be circumvented for generic code. Users are free to bring these hash
implementations to namespace std after specialization for their own
non-std and non-native types.

Change-Id: Ifd0f0b64e5421d5d44890eb25428cc9c53484eb3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67663
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-07-07 10:17:54 +00:00
Gabriel Busnot
5282fac317 base: define is_std_hash_enabled type trait
Change-Id: I7ffb7f80a90006d6b8cd42bdf3d63e34c6dbda01
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71839
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
2023-07-07 10:17:54 +00:00
Gabriel Busnot
2f327fa2b8 base: define is_iterable type trait
Change-Id: I38bb0ddcbb95645797f1d20724b78aff3bef4580
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71838
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2023-07-07 10:17:54 +00:00
Gabriel Busnot
91b4540477 python: Fix namespaced enums params code generation
The wrapper_name parameter was not properly handled. Enums were always
generated in the enums namespace even if required differently by
wrapper_name.

Change-Id: I366846ce39dfe10effc2cc145e7772a3fd171b92
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67662
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
2023-07-07 10:17:54 +00:00
Gabriel Busnot
159953080a mem-ruby: Fix of an address bug in MESI_Two_Level-dir.sm
Physical access address and line address were mixed up in
qw_queueMemoryWBRequest_partial

Change-Id: I0b238ffc59d2bb3de221d96905c75b7616eac964
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67661
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2023-07-07 10:17:54 +00:00
Gabriel Busnot
20dd444273 mem-ruby: Switch to dequeueMemRspQueue() in all Ruby protocols
Change-Id: I33bca345d985618e3fca62e9ddd5bcc3ad8226a3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67659
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
2023-07-07 10:17:54 +00:00