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misc: Merge branch 'stable' into 'develop'

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This ensures all commits in v23.0 are now in the develop branch.

Change-Id: I791346115dd123f3541a3c8060482e00cf4dbfb5
This commit is contained in:
Bobby R. Bruce
2023-07-10 12:24:27 -07:00
parent 9b9dc09f6e 1db206b9d3
commit 54501c3e2b
10 changed files with 151 additions and 20 deletions
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2
src/Doxyfile
View File

@@ -31,7 +31,7 @@ PROJECT_NAME = gem5
# This could be handy for archiving the generated documentation or
# if some version control system is used.
PROJECT_NUMBER = [DEVELOP-FOR-23.0]
PROJECT_NUMBER = v23.0.0.0
# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute)
# base path where the generated documentation will be put.

21
src/arch/arm/regs/misc.cc
View File

@@ -3911,83 +3911,104 @@ ISA::initializeMiscRegMetadata()
.mapsTo(MISCREG_MIDR);
InitReg(MISCREG_MPIDR_EL1)
.allPrivileges().exceptUserMode().writes(0)
.faultRead(EL0, faultIdst)
.mapsTo(MISCREG_MPIDR);
InitReg(MISCREG_REVIDR_EL1)
.faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid1))
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_PFR0_EL1)
.allPrivileges().exceptUserMode().writes(0)
.faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.mapsTo(MISCREG_ID_PFR0);
InitReg(MISCREG_ID_PFR1_EL1)
.allPrivileges().exceptUserMode().writes(0)
.faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.mapsTo(MISCREG_ID_PFR1);
InitReg(MISCREG_ID_DFR0_EL1)
.allPrivileges().exceptUserMode().writes(0)
.faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.mapsTo(MISCREG_ID_DFR0);
InitReg(MISCREG_ID_AFR0_EL1)
.allPrivileges().exceptUserMode().writes(0)
.faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.mapsTo(MISCREG_ID_AFR0);
InitReg(MISCREG_ID_MMFR0_EL1)
.allPrivileges().exceptUserMode().writes(0)
.faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.mapsTo(MISCREG_ID_MMFR0);
InitReg(MISCREG_ID_MMFR1_EL1)
.allPrivileges().exceptUserMode().writes(0)
.faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.mapsTo(MISCREG_ID_MMFR1);
InitReg(MISCREG_ID_MMFR2_EL1)
.allPrivileges().exceptUserMode().writes(0)
.faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.mapsTo(MISCREG_ID_MMFR2);
InitReg(MISCREG_ID_MMFR3_EL1)
.allPrivileges().exceptUserMode().writes(0)
.faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.mapsTo(MISCREG_ID_MMFR3);
InitReg(MISCREG_ID_MMFR4_EL1)
.allPrivileges().exceptUserMode().writes(0)
.faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.mapsTo(MISCREG_ID_MMFR4);
InitReg(MISCREG_ID_ISAR0_EL1)
.allPrivileges().exceptUserMode().writes(0)
.faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.mapsTo(MISCREG_ID_ISAR0);
InitReg(MISCREG_ID_ISAR1_EL1)
.allPrivileges().exceptUserMode().writes(0)
.faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.mapsTo(MISCREG_ID_ISAR1);
InitReg(MISCREG_ID_ISAR2_EL1)
.allPrivileges().exceptUserMode().writes(0)
.faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.mapsTo(MISCREG_ID_ISAR2);
InitReg(MISCREG_ID_ISAR3_EL1)
.allPrivileges().exceptUserMode().writes(0)
.faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.mapsTo(MISCREG_ID_ISAR3);
InitReg(MISCREG_ID_ISAR4_EL1)
.allPrivileges().exceptUserMode().writes(0)
.faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.mapsTo(MISCREG_ID_ISAR4);
InitReg(MISCREG_ID_ISAR5_EL1)
.allPrivileges().exceptUserMode().writes(0)
.faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.mapsTo(MISCREG_ID_ISAR5);
InitReg(MISCREG_ID_ISAR6_EL1)
.allPrivileges().exceptUserMode().writes(0)
.faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.mapsTo(MISCREG_ID_ISAR6);
InitReg(MISCREG_MVFR0_EL1)
.faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.allPrivileges().exceptUserMode().writes(0)
.mapsTo(MISCREG_MVFR0);
InitReg(MISCREG_MVFR1_EL1)
.faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.allPrivileges().exceptUserMode().writes(0)
.mapsTo(MISCREG_MVFR1);
InitReg(MISCREG_MVFR2_EL1)
.faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_AA64PFR0_EL1)

1
src/arch/generic/isa.hh
View File

@@ -70,6 +70,7 @@ class BaseISA : public SimObject
public:
virtual PCStateBase *newPCState(Addr new_inst_addr=0) const = 0;
virtual void clear() {}
virtual void clearLoadReservation(ContextID cid) {}
virtual RegVal readMiscRegNoEffect(RegIndex idx) const = 0;
virtual RegVal readMiscReg(RegIndex idx) = 0;

7
src/arch/riscv/isa.hh
View File

@@ -92,6 +92,13 @@ class ISA : public BaseISA
return new PCState(new_inst_addr, rv_type);
}
void
clearLoadReservation(ContextID cid) override
{
Addr& load_reservation_addr = load_reservation_addrs[cid];
load_reservation_addr = INVALID_RESERVATION_ADDR;
}
public:
RegVal readMiscRegNoEffect(RegIndex idx) const override;
RegVal readMiscReg(RegIndex idx) override;

2
src/base/version.cc
View File

@@ -32,6 +32,6 @@ namespace gem5
/**
* @ingroup api_base_utils
*/
const char *gem5Version = "[DEVELOP-FOR-23.0]";
const char *gem5Version = "23.0.0.0";
} // namespace gem5

10
src/python/gem5/simulate/simulator.py
View File

@@ -53,10 +53,6 @@ class Simulator:
"""
This Simulator class is used to manage the execution of a gem5 simulation.
**Warning:** The simulate package is still in a beta state. The gem5
project does not guarantee the APIs within this package will remain
consistent in future across upcoming releases.
Example
-------
Examples using the Simulator class can be found under
@@ -165,12 +161,6 @@ class Simulator:
"""
warn(
"The simulate package is still in a beta state. The gem5 "
"project does not guarantee the APIs within this package will "
"remain consistent across upcoming releases."
)
# We specify a dictionary here outlining the default behavior for each
# exit event. Each exit event is mapped to a generator.
self._default_on_exit_dict = {