diff --git a/RELEASE-NOTES.md b/RELEASE-NOTES.md index 931be695ba..0c158ee245 100644 --- a/RELEASE-NOTES.md +++ b/RELEASE-NOTES.md @@ -1,3 +1,121 @@ +# Version 23.0 + +This release has approximately 500 contributions from 50 unique contributors. +Below we highlight key gem5 features and improvements in this release. + +## Significant API and user-facing changes + +### Major renaming of CPU stats + +The CPU stats have been renamed. +See for details. + +Now, each stage (fetch, execute, commit) have their own stat group. +Stats that are shared between the different CPU model (O3, Minor, Simple) now have the exact same names. + +**Important:** Some stat names were misleading before this change. +With this change, stats with the same names between different CPU models have the same meaning. + +### `fs.py` and `se.py` deprecated + +These scripts have not been well supported for many gem5 releases. +With gem5 23.0, we have officially deprecated these scripts. +They have been moved into the `deprecated` directory, **but they will be removed in a future release.** +As a replacement, we strongly suggest using the gem5 standard library. +See for more information. + +### Renaming of `DEBUG` guard into `GEM5_DEBUG` + +Scons no longer defines the `DEBUG` guard in debug builds, so code making using of it should use `GEM5_DEBUG` instead. + +### Other API changes + +Also, this release: + +- Removes deprecated namespaces. Namespace names were updated a couple of releases ago. This release removes the old names. +- Uses `MemberEventWrapper` in favor of `EventWrapper` for instance member functions. +- Adds an extension mechanism to `Packet` and `Request`. +- Sets x86 CPU vendor string to "HygoneGenuine" to better support GLIBC. + +## New features and improvements + +### Large improvements to gem5 resources and gem5 resources website + +We now have a new web portal for the gem5 resources: + +This web portal will allow users to browse the resources available (e.g., disk images, kernels, workloads, binaries, simpoints, etc.) to use out-of-the-box with the gem5 standard library. +You can filter based on architecture, resource type, and compatible gem5 versions. + +For each resource, there are examples of how to use the resource and pointers to examples using the resource in the gem5 codebase. + +More information can be found on gem5's website: + +We will be expanding gem5 resources with more workloads and resources over the course of the next release. +If you would like to contribute to gem5 resources by uploading your own workloads, disk images, etc., please create an issue on GitHub. + +In addition to the new gem5 Resources web portal, the gem5 Resources API has been significantly updated and improved. +There are now much simpler functions for getting resources such as `obtain_resource()` that will download the resource by name and return a reference that can be used (e.g., as a binary in `set_se_workload` function on the board). +As such the generic `Resouce` class has been deprecated and will be removed in a future release. + +Resources are now specialized for their particular category. +For example, there is now a `BinaryResource` class which will return if a user specifies a binary resource when using the `obtain_resource` function. +This allow for resource typing and for greater resource specialization. + +### Arm ISA improvements + +Architectural support for Armv9 [Scalable Matrix extension](https://developer.arm.com/documentation/ddi0616/latest) (FEAT_SME). +The implementation employs a simple renaming scheme for the Za array register in the O3 CPU, so that writes to difference tiles in the register are considered a dependency and are therefore serialized. + +The following SVE and SIMD & FP extensions have also been implemented: +* FEAT_F64MM +* FEAT_F32MM +* FEAT_DOTPROD +* FEAT_I8MM + +And more generally: + +* FEAT_TLBIOS +* FEAT_FLAGM +* FEAT_FLAGM2 +* FEAT_RNG +* FEAT_RNG_TRAP +* FEAT_EVT + +### Support for DRAMSys + +gem5 can now use DRAMSys as a DRAM backend. + +### RISC-V improvements + +This release: + +- Fully implements RISC-V scalar cryptography extensions. +- Fully implement RISC-V rv32. +- Implements PMP lock features. +- Adds general RISC-V improvements to provide better stability. + +### Standard library improvements and new components + +This release: + +- Adds MESI_Three_Level component. +- Supports ELFies and LoopPoint analysis output from Sniper. +- Supports DRAMSys in the stdlib. + +## Bugfixes and other small improvements + +This release also: + +- Removes deprecated python libraries. +- Adds a DDR5 model. +- Adds AMD GPU MI200/gfx90a support. +- Changes building so it no longer "duplicates sources" in build/ which improves support for some IDEs and code analysis. If you still need to duplicate sources you can use the `--duplicate-sources` option to `scons`. +- Enables `--debug-activate=` to use debug trace for only a single SimObject (the opposite of `--debug-ignore`). See `--debug-help` for more information. +- Adds support to exit the simulation loop based on Arm-PMU events. +- Supports Python 3.11. +- Adds the idea of a CpuCluster to gem5. + + # Version 22.1.0.0 This release has 500 contributions from 48 unique contributors and marks our second major release of 2022. diff --git a/SConstruct b/SConstruct index 9b25b33783..4fe2f64366 100755 --- a/SConstruct +++ b/SConstruct @@ -447,12 +447,6 @@ for variant_path in variant_paths: conf.CheckLinkFlag( '-Wl,--thread-count=%d' % GetOption('num_jobs')) - # Treat warnings as errors but white list some warnings that we - # want to allow (e.g., deprecation warnings). - env.Append(CCFLAGS=['-Werror', - '-Wno-error=deprecated-declarations', - '-Wno-error=deprecated', - ]) else: error('\n'.join(( diff --git a/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py b/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py index 60d93ebe77..10d5da0adb 100644 --- a/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py +++ b/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py @@ -262,7 +262,7 @@ board.set_kernel_disk_workload( kernel=Resource("x86-linux-kernel-4.19.83"), # The location of the x86 SPEC CPU 2017 image disk_image=CustomDiskImageResource( - args.image, disk_root_partition=args.partition + args.image, root_partition=args.partition ), readfile_contents=command, ) diff --git a/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py b/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py index c491c9bce9..cb5f5d19e3 100644 --- a/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py +++ b/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py @@ -278,7 +278,7 @@ board.set_kernel_disk_workload( kernel=Resource("x86-linux-kernel-4.19.83"), # The location of the x86 SPEC CPU 2017 image disk_image=CustomDiskImageResource( - args.image, disk_root_partition=args.partition + args.image, root_partition=args.partition ), readfile_contents=command, ) diff --git a/src/Doxyfile b/src/Doxyfile index 24d70bbc55..325040fee0 100644 --- a/src/Doxyfile +++ b/src/Doxyfile @@ -31,7 +31,7 @@ PROJECT_NAME = gem5 # This could be handy for archiving the generated documentation or # if some version control system is used. -PROJECT_NUMBER = [DEVELOP-FOR-23.0] +PROJECT_NUMBER = v23.0.0.0 # The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) # base path where the generated documentation will be put. diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index f32aa7230c..f1c69cc007 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -3911,83 +3911,104 @@ ISA::initializeMiscRegMetadata() .mapsTo(MISCREG_MIDR); InitReg(MISCREG_MPIDR_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .mapsTo(MISCREG_MPIDR); InitReg(MISCREG_REVIDR_EL1) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid1)) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_ID_PFR0_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_PFR0); InitReg(MISCREG_ID_PFR1_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_PFR1); InitReg(MISCREG_ID_DFR0_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_DFR0); InitReg(MISCREG_ID_AFR0_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_AFR0); InitReg(MISCREG_ID_MMFR0_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_MMFR0); InitReg(MISCREG_ID_MMFR1_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_MMFR1); InitReg(MISCREG_ID_MMFR2_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_MMFR2); InitReg(MISCREG_ID_MMFR3_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_MMFR3); InitReg(MISCREG_ID_MMFR4_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_MMFR4); InitReg(MISCREG_ID_ISAR0_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_ISAR0); InitReg(MISCREG_ID_ISAR1_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_ISAR1); InitReg(MISCREG_ID_ISAR2_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_ISAR2); InitReg(MISCREG_ID_ISAR3_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_ISAR3); InitReg(MISCREG_ID_ISAR4_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_ISAR4); InitReg(MISCREG_ID_ISAR5_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_ISAR5); InitReg(MISCREG_ID_ISAR6_EL1) .allPrivileges().exceptUserMode().writes(0) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .mapsTo(MISCREG_ID_ISAR6); InitReg(MISCREG_MVFR0_EL1) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .allPrivileges().exceptUserMode().writes(0) .mapsTo(MISCREG_MVFR0); InitReg(MISCREG_MVFR1_EL1) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .allPrivileges().exceptUserMode().writes(0) .mapsTo(MISCREG_MVFR1); InitReg(MISCREG_MVFR2_EL1) + .faultRead(EL0, faultIdst) .faultRead(EL1, HCR_TRAP(tid3)) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_ID_AA64PFR0_EL1) diff --git a/src/arch/generic/isa.hh b/src/arch/generic/isa.hh index e9e4d95d7b..58f66fc99b 100644 --- a/src/arch/generic/isa.hh +++ b/src/arch/generic/isa.hh @@ -70,6 +70,7 @@ class BaseISA : public SimObject public: virtual PCStateBase *newPCState(Addr new_inst_addr=0) const = 0; virtual void clear() {} + virtual void clearLoadReservation(ContextID cid) {} virtual RegVal readMiscRegNoEffect(RegIndex idx) const = 0; virtual RegVal readMiscReg(RegIndex idx) = 0; diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh index 31001c04b4..352a8eb0cd 100644 --- a/src/arch/riscv/isa.hh +++ b/src/arch/riscv/isa.hh @@ -92,6 +92,13 @@ class ISA : public BaseISA return new PCState(new_inst_addr, rv_type); } + void + clearLoadReservation(ContextID cid) override + { + Addr& load_reservation_addr = load_reservation_addrs[cid]; + load_reservation_addr = INVALID_RESERVATION_ADDR; + } + public: RegVal readMiscRegNoEffect(RegIndex idx) const override; RegVal readMiscReg(RegIndex idx) override; diff --git a/src/base/version.cc b/src/base/version.cc index 8131a3197e..38f415590a 100644 --- a/src/base/version.cc +++ b/src/base/version.cc @@ -32,6 +32,6 @@ namespace gem5 /** * @ingroup api_base_utils */ -const char *gem5Version = "[DEVELOP-FOR-23.0]"; +const char *gem5Version = "23.0.0.0"; } // namespace gem5 diff --git a/src/python/gem5/simulate/simulator.py b/src/python/gem5/simulate/simulator.py index e27679a996..0551745b36 100644 --- a/src/python/gem5/simulate/simulator.py +++ b/src/python/gem5/simulate/simulator.py @@ -53,10 +53,6 @@ class Simulator: """ This Simulator class is used to manage the execution of a gem5 simulation. - **Warning:** The simulate package is still in a beta state. The gem5 - project does not guarantee the APIs within this package will remain - consistent in future across upcoming releases. - Example ------- Examples using the Simulator class can be found under @@ -165,12 +161,6 @@ class Simulator: """ - warn( - "The simulate package is still in a beta state. The gem5 " - "project does not guarantee the APIs within this package will " - "remain consistent across upcoming releases." - ) - # We specify a dictionary here outlining the default behavior for each # exit event. Each exit event is mapped to a generator. self._default_on_exit_dict = {