Merge branch 'develop' into fix-bitfield-unused

.github/workflows/ci-tests.yaml

@@ -103,6 +103,7 @@ jobs:
           path: output.zip
           retention-days: 7
       - name: Clean runner
+        if: success() || failure()
         run:
           rm -rf ./* || true
           rm -rf ./.??* || true

.github/workflows/utils.yaml

@@ -0,0 +1,19 @@
+# This workflow file contains miscellaneous tasks to manage the repository.
+name: Utils for Repository
+on:
+  schedule:
+    - cron: '30 1 * * *'
+  workflow_dispatch:
+
+jobs:
+  # This job runs the stale action to close issues that have been inactive for 30 days.
+  # It is scheduled to run every day at 1:30 AM UTC.
+  close-stale-issues:
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/stale@v8.0.0
+        with:
+          close-issue-message: 'This issue is being closed because it has been inactive waiting for response for 30 days. If this is still an issue, please open a new issue and reference this one.'
+          days-before-stale: 21
+          days-before-close: 7
+          any-of-labels: 'needs details'

configs/example/gem5_library/arm-hello.py

@@ -43,7 +43,7 @@ scons build/ARM/gem5.opt
 
 from gem5.isas import ISA
 from gem5.utils.requires import requires
-from gem5.resources.resource import Resource
+from gem5.resources.resource import obtain_resource
 from gem5.components.memory import SingleChannelDDR3_1600
 from gem5.components.processors.cpu_types import CPUTypes
 from gem5.components.boards.simple_board import SimpleBoard
@@ -84,7 +84,7 @@ board.set_se_binary_workload(
     # Any resource specified in this file will be automatically retrieved.
     # At the time of writing, this file is a WIP and does not contain all
     # resources. Jira ticket: https://gem5.atlassian.net/browse/GEM5-1096
-    Resource("arm-hello64-static")
+    obtain_resource("arm-hello64-static")
 )
 
 # Lastly we run the simulation.

configs/example/gem5_library/checkpoints/riscv-hello-restore-checkpoint.py

@@ -48,7 +48,7 @@ scons build/RISCV/gem5.opt
 
 from gem5.isas import ISA
 from gem5.utils.requires import requires
-from gem5.resources.resource import Resource
+from gem5.resources.resource import obtain_resource
 from gem5.components.memory import SingleChannelDDR3_1600
 from gem5.components.processors.cpu_types import CPUTypes
 from gem5.components.boards.simple_board import SimpleBoard
@@ -89,8 +89,8 @@ board = SimpleBoard(
 # configs/example/gem5_library/checkpoints/riscv-hello-save-checkpoint.py
 board.set_se_binary_workload(
     # the workload should be the same as the save-checkpoint script
-    Resource("riscv-hello"),
-    checkpoint=Resource("riscv-hello-example-checkpoint-v23"),
+    obtain_resource("riscv-hello"),
+    checkpoint=obtain_resource("riscv-hello-example-checkpoint-v23"),
 )
 
 simulator = Simulator(

configs/example/gem5_library/checkpoints/riscv-hello-save-checkpoint.py

@@ -46,7 +46,7 @@ scons build/RISCV/gem5.opt
 import argparse
 from gem5.isas import ISA
 from gem5.utils.requires import requires
-from gem5.resources.resource import Resource
+from gem5.resources.resource import obtain_resource
 from gem5.components.memory import SingleChannelDDR3_1600
 from gem5.components.processors.cpu_types import CPUTypes
 from gem5.components.boards.simple_board import SimpleBoard
@@ -101,7 +101,7 @@ board.set_se_binary_workload(
     # Any resource specified in this file will be automatically retrieved.
     # At the time of writing, this file is a WIP and does not contain all
     # resources. Jira ticket: https://gem5.atlassian.net/browse/GEM5-1096
-    Resource("riscv-hello")
+    obtain_resource("riscv-hello")
 )
 
 # Lastly we run the simulation.

configs/example/gem5_library/dramsys/arm-hello-dramsys.py

@@ -35,7 +35,7 @@ correctly. If this is not done correctly this script will run with error.
 
 from gem5.isas import ISA
 from gem5.utils.requires import requires
-from gem5.resources.resource import Resource
+from gem5.resources.resource import obtain_resource
 from gem5.components.memory import DRAMSysDDR3_1600
 from gem5.components.processors.cpu_types import CPUTypes
 from gem5.components.boards.simple_board import SimpleBoard
@@ -78,7 +78,7 @@ board.set_se_binary_workload(
     # Any resource specified in this file will be automatically retrieved.
     # At the time of writing, this file is a WIP and does not contain all
     # resources. Jira ticket: https://gem5.atlassian.net/browse/GEM5-1096
-    Resource("arm-hello64-static")
+    obtain_resource("arm-hello64-static")
 )
 
 # Lastly we run the simulation.

configs/example/gem5_library/power-hello.py

@@ -43,7 +43,7 @@ scons build/POWER/gem5.opt
 
 from gem5.isas import ISA
 from gem5.utils.requires import requires
-from gem5.resources.resource import Resource
+from gem5.resources.resource import obtain_resource
 from gem5.components.memory import SingleChannelDDR4_2400
 from gem5.components.processors.cpu_types import CPUTypes
 from gem5.components.boards.simple_board import SimpleBoard
@@ -75,7 +75,7 @@ board = SimpleBoard(
     cache_hierarchy=cache_hierarchy,
 )
 
-board.set_se_binary_workload(Resource("power-hello"))
+board.set_se_binary_workload(obtain_resource("power-hello"))
 
 # Lastly we run the simulation.
 simulator = Simulator(board=board)

configs/example/gem5_library/riscv-fs.py

@@ -48,7 +48,7 @@ from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierar
 from gem5.components.processors.cpu_types import CPUTypes
 from gem5.isas import ISA
 from gem5.utils.requires import requires
-from gem5.resources.resource import Resource
+from gem5.resources.resource import obtain_resource
 from gem5.simulate.simulator import Simulator
 
 # Run a check to ensure the right version of gem5 is being used.
@@ -79,8 +79,8 @@ board = RiscvBoard(
 
 # Set the Full System workload.
 board.set_kernel_disk_workload(
-    kernel=Resource("riscv-bootloader-vmlinux-5.10"),
-    disk_image=Resource("riscv-disk-img"),
+    kernel=obtain_resource("riscv-bootloader-vmlinux-5.10"),
+    disk_image=obtain_resource("riscv-disk-img"),
 )
 
 simulator = Simulator(board=board)

configs/example/gem5_library/riscvmatched-hello.py

@@ -37,7 +37,7 @@ scons build/RISCV/gem5.opt
 ```
 """
 
-from gem5.resources.resource import Resource
+from gem5.resources.resource import obtain_resource
 from gem5.simulate.simulator import Simulator
 from gem5.prebuilt.riscvmatched.riscvmatched_board import RISCVMatchedBoard
 from gem5.isas import ISA
@@ -49,7 +49,7 @@ requires(isa_required=ISA.RISCV)
 board = RISCVMatchedBoard()
 
 # set the hello world riscv binary as the board workload
-board.set_se_binary_workload(Resource("riscv-hello"))
+board.set_se_binary_workload(obtain_resource("riscv-hello"))
 
 # run the simulation with the RISCV Matched board
 simulator = Simulator(board=board, full_system=False)

configs/example/gem5_library/x86-gapbs-benchmarks.py

@@ -63,7 +63,7 @@ from gem5.components.processors.simple_switchable_processor import (
 from gem5.components.processors.cpu_types import CPUTypes
 from gem5.isas import ISA
 from gem5.coherence_protocol import CoherenceProtocol
-from gem5.resources.resource import Resource
+from gem5.resources.resource import obtain_resource
 from gem5.simulate.simulator import Simulator
 from gem5.simulate.exit_event import ExitEvent
 
@@ -203,10 +203,10 @@ board.set_kernel_disk_workload(
     # The x86 linux kernel will be automatically downloaded to the
     # `~/.cache/gem5` directory if not already present.
     # gapbs benchamarks was tested with kernel version 4.19.83
-    kernel=Resource("x86-linux-kernel-4.19.83"),
+    kernel=obtain_resource("x86-linux-kernel-4.19.83"),
     # The x86-gapbs image will be automatically downloaded to the
     # `~/.cache/gem5` directory if not already present.
-    disk_image=Resource("x86-gapbs"),
+    disk_image=obtain_resource("x86-gapbs"),
     readfile_contents=command,
 )
 

configs/example/gem5_library/x86-npb-benchmarks.py

@@ -60,7 +60,7 @@ from gem5.components.processors.simple_switchable_processor import (
 from gem5.components.processors.cpu_types import CPUTypes
 from gem5.isas import ISA
 from gem5.coherence_protocol import CoherenceProtocol
-from gem5.resources.resource import Resource
+from gem5.resources.resource import obtain_resource
 from gem5.simulate.simulator import Simulator
 from gem5.simulate.simulator import ExitEvent
 
@@ -204,10 +204,10 @@ board.set_kernel_disk_workload(
     # The x86 linux kernel will be automatically downloaded to the
     # `~/.cache/gem5` directory if not already present.
     # npb benchamarks was tested with kernel version 4.19.83
-    kernel=Resource("x86-linux-kernel-4.19.83"),
+    kernel=obtain_resource("x86-linux-kernel-4.19.83"),
     # The x86-npb image will be automatically downloaded to the
     # `~/.cache/gem5` directory if not already present.
-    disk_image=Resource("x86-npb"),
+    disk_image=obtain_resource("x86-npb"),
     readfile_contents=command,
 )
 

configs/example/gem5_library/x86-parsec-benchmarks.py

@@ -59,7 +59,7 @@ from gem5.components.processors.simple_switchable_processor import (
 from gem5.components.processors.cpu_types import CPUTypes
 from gem5.isas import ISA
 from gem5.coherence_protocol import CoherenceProtocol
-from gem5.resources.resource import Resource
+from gem5.resources.resource import obtain_resource
 from gem5.simulate.simulator import Simulator
 from gem5.simulate.exit_event import ExitEvent
 
@@ -185,10 +185,10 @@ board.set_kernel_disk_workload(
     # The x86 linux kernel will be automatically downloaded to the
     # `~/.cache/gem5` directory if not already present.
     # PARSEC benchamarks were tested with kernel version 4.19.83
-    kernel=Resource("x86-linux-kernel-4.19.83"),
+    kernel=obtain_resource("x86-linux-kernel-4.19.83"),
     # The x86-parsec image will be automatically downloaded to the
     # `~/.cache/gem5` directory if not already present.
-    disk_image=Resource("x86-parsec"),
+    disk_image=obtain_resource("x86-parsec"),
     readfile_contents=command,
 )
 

configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py

@@ -65,7 +65,7 @@ from gem5.components.processors.simple_switchable_processor import (
 from gem5.components.processors.cpu_types import CPUTypes
 from gem5.isas import ISA
 from gem5.coherence_protocol import CoherenceProtocol
-from gem5.resources.resource import Resource, CustomDiskImageResource
+from gem5.resources.resource import Resource, DiskImageResource
 from gem5.simulate.simulator import Simulator
 from gem5.simulate.exit_event import ExitEvent
 
@@ -261,9 +261,7 @@ board.set_kernel_disk_workload(
     # 5.4.49
     kernel=Resource("x86-linux-kernel-4.19.83"),
     # The location of the x86 SPEC CPU 2017 image
-    disk_image=CustomDiskImageResource(
-        args.image, root_partition=args.partition
-    ),
+    disk_image=DiskImageResource(args.image, root_partition=args.partition),
     readfile_contents=command,
 )
 

configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py

@@ -63,7 +63,7 @@ from gem5.components.processors.simple_switchable_processor import (
 from gem5.components.processors.cpu_types import CPUTypes
 from gem5.isas import ISA
 from gem5.coherence_protocol import CoherenceProtocol
-from gem5.resources.resource import Resource, CustomDiskImageResource
+from gem5.resources.resource import obtain_resource, DiskImageResource
 from gem5.simulate.simulator import Simulator
 from gem5.simulate.exit_event import ExitEvent
 
@@ -268,18 +268,16 @@ except FileExistsError:
 
 command = f"{args.benchmark} {args.size} {output_dir}"
 
-# For enabling CustomResource, we pass an additional parameter to mount the
+# For enabling DiskImageResource, we pass an additional parameter to mount the
 # correct partition.
 
 board.set_kernel_disk_workload(
     # The x86 linux kernel will be automatically downloaded to the
     # `~/.cache/gem5` directory if not already present.
     # SPEC CPU2017 benchamarks were tested with kernel version 4.19.83
-    kernel=Resource("x86-linux-kernel-4.19.83"),
+    kernel=obtain_resource("x86-linux-kernel-4.19.83"),
     # The location of the x86 SPEC CPU 2017 image
-    disk_image=CustomDiskImageResource(
-        args.image, root_partition=args.partition
-    ),
+    disk_image=DiskImageResource(args.image, root_partition=args.partition),
     readfile_contents=command,
 )
 

configs/example/lupv/run_lupv.py

@@ -42,7 +42,7 @@ from gem5.components.processors.simple_processor import SimpleProcessor
 from gem5.components.processors.cpu_types import CPUTypes
 from gem5.isas import ISA
 from gem5.utils.requires import requires
-from gem5.resources.resource import Resource, CustomResource
+from gem5.resources.resource import obtain_resource
 
 import argparse
 
@@ -98,8 +98,8 @@ board = LupvBoard(
 # Set the Full System workload.
 
 board.set_kernel_disk_workload(
-    kernel=Resource("riscv-lupio-linux-kernel"),
-    disk_image=Resource("riscv-lupio-busybox-img"),
+    kernel=obtain_resource("riscv-lupio-linux-kernel"),
+    disk_image=obtain_resource("riscv-lupio-busybox-img"),
 )
 
 

configs/example/sst/riscv_fs.py

@@ -29,7 +29,7 @@ from m5.objects import *
 from os import path
 
 # For downloading the disk image
-from gem5.resources.resource import Resource
+from gem5.resources.resource import obtain_resource
 
 import argparse
 
@@ -139,7 +139,7 @@ cpu_clock_rate = args.cpu_clock_rate
 memory_size = args.memory_size
 
 # Try downloading the Resource
-bbl_resource = Resource("riscv-boot-exit-nodisk")
+bbl_resource = obtain_resource("riscv-boot-exit-nodisk")
 bbl_path = bbl_resource.get_local_path()
 
 system = System()

configs/ruby/GPU_VIPER.py

@@ -489,6 +489,9 @@ def define_options(parser):
         help="Size of the mandatory queue in the GPU scalar "
         "cache controller",
     )
+    parser.add_argument(
+        "--glc-atomic-latency", type=int, default=1, help="GLC Atomic Latency"
+    )
 
 
 def construct_dirs(options, system, ruby_system, network):
@@ -875,6 +878,7 @@ def construct_tccs(options, system, ruby_system, network):
         tcc_cntrl.create(options, ruby_system, system)
         tcc_cntrl.l2_request_latency = options.gpu_to_dir_latency
         tcc_cntrl.l2_response_latency = options.TCC_latency
+        tcc_cntrl.glc_atomic_latency = options.glc_atomic_latency
         tcc_cntrl_nodes.append(tcc_cntrl)
         tcc_cntrl.WB = options.WB_L2
         tcc_cntrl.number_of_TBEs = 2560 * options.num_compute_units

src/base/cprintf_formats.hh

@@ -34,6 +34,8 @@
 #include <ostream>
 #include <sstream>
 
+#include "base/stl_helpers.hh"
+
 namespace gem5
 {
 
@@ -221,6 +223,7 @@ template <typename T>
 static inline void
 _formatString(std::ostream &out, const T &data, Format &fmt)
 {
+    using stl_helpers::operator<<;
     if (fmt.width > 0) {
         std::stringstream foo;
         foo << data;

src/base/stl_helpers/ostream_helpers.hh

@@ -41,6 +41,19 @@
 namespace gem5::stl_helpers
 {
 
+/*
+ * Wrap any object in a Printer object to force using a opExtract_impl printing
+ * function. This is not required for types that do not already enable
+ * operator<< in another namespace. However, to enable the special printing
+ * function for, e.g., raw pointers, those must be wrapped in a Printer.
+ */
+template<typename T>
+struct Printer
+{
+    Printer(const T& value): value{value} {}
+    const T& value;
+};
+
 namespace opExtract_impl
 {
 
@@ -51,7 +64,7 @@ namespace opExtract_impl
  * mechanism is used. The only entry point in the system is through a primary
  * dispatch function that won't resolve for non-helped types. Then, recursive
  * calls go through the secondary dispatch interface that sort between helped
- * and non-helped types. Helped typed will enter the system back through the
+ * and non-helped types. Helped types will enter the system back through the
  * primary dispatch interface while other types will look for operator<<
  * through regular lookup, especially ADL.
  */
@@ -106,7 +119,7 @@ opExtractPrimDisp(std::ostream& os, const std::optional<T>& o)
     if (o) {
         return opExtractSecDisp(os, *o);
     } else {
-        return os << '-';
+        return os << "(-)";
     }
 }
 
@@ -128,6 +141,10 @@ opExtractPrimDisp(std::ostream& os, const std::unique_ptr<T>& p)
     return opExtractPrimDisp(os, p.get());
 }
 
+template <typename T>
+std::ostream&
+opExtractPrimDisp(std::ostream& os, const Printer<T>& p);
+
 template <typename, typename = void>
 constexpr bool isOpExtractNativelySupported = false;
 
@@ -166,6 +183,18 @@ opExtractPrimDisp(std::ostream& os, T* p)
     }
 }
 
+template <typename T>
+std::ostream&
+opExtractPrimDisp(std::ostream& os, const Printer<T>& p)
+{
+    if constexpr (isOpExtractHelped<T>) {
+        return opExtractPrimDisp(os, p.value);
+    } else {
+        return os << p.value;
+    }
+}
+
+
 template<typename T>
 std::ostream&
 opExtractSecDisp(std::ostream& os, const T& v)
@@ -179,7 +208,8 @@ opExtractSecDisp(std::ostream& os, const T& v)
 
 } // namespace opExtract_impl
 
-// Add "using stl_helpers::operator<<" in the scope where you want to use it.
+// use the Printer wrapper or add "using stl_helpers::operator<<" in the scope
+// where you want to use that operator<<.
 template<typename T>
 std::enable_if_t<opExtract_impl::needsDispatch<T>, std::ostream&>
 operator<<(std::ostream& os, const T& v)

src/base/stl_helpers/ostream_helpers.test.cc

@@ -34,9 +34,9 @@
 
 #include "base/stl_helpers/ostream_helpers.hh"
 
-using gem5::stl_helpers::operator<<;
 
 TEST(OstreamHelpers, pair) {
+    using gem5::stl_helpers::operator<<;
     auto p = std::make_pair(1, 2);
     std::ostringstream os;
     os << p;
@@ -44,6 +44,7 @@ TEST(OstreamHelpers, pair) {
 }
 
 TEST(OstreamHelpers, tuple) {
+    using gem5::stl_helpers::operator<<;
     auto t = std::make_tuple(true,
         std::make_pair("Hello", std::string_view("World")), '!');
     std::ostringstream os;
@@ -52,6 +53,7 @@ TEST(OstreamHelpers, tuple) {
 }
 
 TEST(OstreamHelpers, vector) {
+    using gem5::stl_helpers::operator<<;
     auto v = std::vector<const char*>{"abc", "defg", "hijklm", "\n"};
     std::ostringstream os;
     os << v;
@@ -59,8 +61,58 @@ TEST(OstreamHelpers, vector) {
 }
 
 TEST(OstreamHelpers, map) {
+    using gem5::stl_helpers::operator<<;
     auto m = std::map<char, int>{{'a', 0}, {'b', 1}, {'c', 2}, {'d', 3}};
     std::ostringstream os;
     os << m;
     EXPECT_EQ(os.str(), "[ (a, 0), (b, 1), (c, 2), (d, 3), ]");
 }
+
+TEST(OstreamHelpers, optional) {
+    using gem5::stl_helpers::operator<<;
+    auto m = std::make_optional<int>(42);
+    std::ostringstream os;
+    os << m;
+    EXPECT_EQ(os.str(), "42");
+    os.str("");
+    m.reset();
+    os << m;
+    EXPECT_EQ(os.str(), "(-)");
+}
+
+TEST(OstreamHelpers, printer) {
+    std::string hello = "Hello";
+    std::ostringstream os;
+    os << hello;
+    EXPECT_EQ(os.str(), hello);
+
+    std::ostringstream os2;
+    os2 << gem5::stl_helpers::Printer(hello);
+    EXPECT_EQ(os2.str(), "[ H, e, l, l, o, ]");
+}
+
+
+TEST(OstreamHelpers, pointers) {
+    auto helped_representation = [](const auto& val) {
+        std::ostringstream os;
+        os << gem5::stl_helpers::Printer(val);
+        return os.str();
+    };
+    auto expected_representation = [&](const auto& ptr) {
+        using gem5::stl_helpers::operator<<;
+        std::ostringstream os;
+        auto* raw_ptr = &*ptr;
+        os << '(' << raw_ptr << ": " << *ptr << ')';
+        return os.str();
+    };
+
+    int x = 42;
+    auto* ptr = &x;
+    EXPECT_EQ(helped_representation(ptr), expected_representation(ptr));
+
+    auto uptr = std::make_unique<std::string>("Hello, World!");
+    EXPECT_EQ(helped_representation(uptr), expected_representation(uptr));
+
+    auto sptr = std::make_shared<std::optional<bool>>();
+    EXPECT_EQ(helped_representation(sptr), expected_representation(sptr));
+}

src/mem/ruby/network/MessageBuffer.cc

@@ -62,7 +62,8 @@ MessageBuffer::MessageBuffer(const Params &p)
     m_max_dequeue_rate(p.max_dequeue_rate), m_dequeues_this_cy(0),
     m_time_last_time_size_checked(0),
     m_time_last_time_enqueue(0), m_time_last_time_pop(0),
-    m_last_arrival_time(0), m_strict_fifo(p.ordered),
+    m_last_arrival_time(0), m_last_message_strict_fifo_bypassed(false),
+    m_strict_fifo(p.ordered),
     m_randomization(p.randomization),
     m_allow_zero_latency(p.allow_zero_latency),
     m_routing_priority(p.routing_priority),
@@ -214,7 +215,8 @@ random_time()
 }
 
 void
-MessageBuffer::enqueue(MsgPtr message, Tick current_time, Tick delta)
+MessageBuffer::enqueue(MsgPtr message, Tick current_time, Tick delta,
+                       bool bypassStrictFIFO)
 {
     // record current time incase we have a pop that also adjusts my size
     if (m_time_last_time_enqueue < current_time) {
@@ -252,7 +254,8 @@ MessageBuffer::enqueue(MsgPtr message, Tick current_time, Tick delta)
 
     // Check the arrival time
     assert(arrival_time >= current_time);
-    if (m_strict_fifo) {
+    if (m_strict_fifo &&
+        !(bypassStrictFIFO || m_last_message_strict_fifo_bypassed)) {
         if (arrival_time < m_last_arrival_time) {
             panic("FIFO ordering violated: %s name: %s current time: %d "
                   "delta: %d arrival_time: %d last arrival_time: %d\n",
@@ -266,6 +269,8 @@ MessageBuffer::enqueue(MsgPtr message, Tick current_time, Tick delta)
         m_last_arrival_time = arrival_time;
     }
 
+    m_last_message_strict_fifo_bypassed = bypassStrictFIFO;
+
     // compute the delay cycles and set enqueue time
     Message* msg_ptr = message.get();
     assert(msg_ptr != NULL);

src/mem/ruby/network/MessageBuffer.hh

@@ -123,7 +123,8 @@ class MessageBuffer : public SimObject
 
     const MsgPtr &peekMsgPtr() const { return m_prio_heap.front(); }
 
-    void enqueue(MsgPtr message, Tick curTime, Tick delta);
+    void enqueue(MsgPtr message, Tick curTime, Tick delta,
+                bool bypassStrictFIFO = false);
 
     // Defer enqueueing a message to a later cycle by putting it aside and not
     // enqueueing it in this cycle
@@ -271,6 +272,9 @@ class MessageBuffer : public SimObject
 
     uint64_t m_msg_counter;
     int m_priority_rank;
+
+    bool m_last_message_strict_fifo_bypassed;
+
     const bool m_strict_fifo;
     const MessageRandomization m_randomization;
     const bool m_allow_zero_latency;

src/mem/ruby/protocol/GPU_VIPER-TCC.sm

@@ -36,6 +36,7 @@ machine(MachineType:TCC, "TCC Cache")
    bool WB; /*is this cache Writeback?*/
    Cycles l2_request_latency := 50;
    Cycles l2_response_latency := 20;
+   Cycles glc_atomic_latency := 0;
 
   // From the TCPs or SQCs
   MessageBuffer * requestFromTCP, network="From", virtual_network="1", vnet_type="request";
@@ -510,7 +511,7 @@ machine(MachineType:TCC, "TCC Cache")
 
   action(ar_sendAtomicResponse, "ar", desc="send Atomic Ack") {
     peek(coreRequestNetwork_in, CPURequestMsg) {
-        enqueue(responseToCore_out, ResponseMsg, l2_response_latency) {
+        enqueue(responseToCore_out, ResponseMsg, l2_response_latency + glc_atomic_latency, true) {
           out_msg.addr := address;
           out_msg.Type := CoherenceResponseType:TDSysResp;
           out_msg.Destination.clear();

src/mem/slicc/ast/EnqueueStatementAST.py

@@ -31,12 +31,21 @@ from slicc.symbols import Var
 
 
 class EnqueueStatementAST(StatementAST):
-    def __init__(self, slicc, queue_name, type_ast, lexpr, statements):
+    def __init__(
+        self,
+        slicc,
+        queue_name,
+        type_ast,
+        lexpr,
+        bypass_strict_fifo,
+        statements,
+    ):
         super().__init__(slicc)
 
         self.queue_name = queue_name
         self.type_ast = type_ast
         self.latexpr = lexpr
+        self.bypass_strict_fifo = bypass_strict_fifo
         self.statements = statements
 
     def __repr__(self):
@@ -76,10 +85,17 @@ class EnqueueStatementAST(StatementAST):
 
         if self.latexpr != None:
             ret_type, rcode = self.latexpr.inline(True)
-            code(
-                "(${{self.queue_name.var.code}}).enqueue("
-                "out_msg, clockEdge(), cyclesToTicks(Cycles($rcode)));"
-            )
+            if self.bypass_strict_fifo != None:
+                bypass_strict_fifo_code = self.bypass_strict_fifo.inline(False)
+                code(
+                    "(${{self.queue_name.var.code}}).enqueue("
+                    "out_msg, clockEdge(), cyclesToTicks(Cycles($rcode)), $bypass_strict_fifo_code);"
+                )
+            else:
+                code(
+                    "(${{self.queue_name.var.code}}).enqueue("
+                    "out_msg, clockEdge(), cyclesToTicks(Cycles($rcode)));"
+                )
         else:
             code(
                 "(${{self.queue_name.var.code}}).enqueue(out_msg, "

src/mem/slicc/parser.py

@@ -633,11 +633,15 @@ class SLICC(Grammar):
 
     def p_statement__enqueue(self, p):
         "statement : ENQUEUE '(' var ',' type ')' statements"
-        p[0] = ast.EnqueueStatementAST(self, p[3], p[5], None, p[7])
+        p[0] = ast.EnqueueStatementAST(self, p[3], p[5], None, None, p[7])
 
     def p_statement__enqueue_latency(self, p):
         "statement : ENQUEUE '(' var ',' type ',' expr ')' statements"
-        p[0] = ast.EnqueueStatementAST(self, p[3], p[5], p[7], p[9])
+        p[0] = ast.EnqueueStatementAST(self, p[3], p[5], p[7], None, p[9])
+
+    def p_statement__enqueue_latency_bypass_strict_fifo(self, p):
+        "statement : ENQUEUE '(' var ',' type ',' expr ',' expr ')' statements"
+        p[0] = ast.EnqueueStatementAST(self, p[3], p[5], p[7], p[9], p[11])
 
     def p_statement__defer_enqueueing(self, p):
         "statement : DEFER_ENQUEUEING '(' var ',' type ')' statements"

src/python/gem5/resources/workload.py

@@ -52,7 +52,7 @@ class AbstractWorkload:
     workload = CustomWorkload(
         function = "set_se_binary_workload",
         parameters = {
-            "binary" : Resource("x86-print-this"),
+            "binary" : obtain_resource("x86-print-this"),
             "arguments" : ["hello", 6]
         },
     )
@@ -64,7 +64,7 @@ class AbstractWorkload:
 
     ```py
     board.set_se_binary_workload(
-        binary = Resource("x86-print-this"),
+        binary = obtain_resource("x86-print-this"),
         arguments = ["hello", 6],
     )
     ```
@@ -121,7 +121,7 @@ class CustomWorkload(AbstractWorkload):
     workload = CustomWorkload(
         function = "set_se_binary_workload",
         parameters = {
-            "binary" : Resource("x86-print-this"),
+            "binary" : obtain_resource("x86-print-this"),
             "arguments" : ["hello", 6]
         },
     )
@@ -148,7 +148,9 @@ class Workload(AbstractWorkload):
 
     # Optionally we can override a parameter in the workload. In this example
     # we are going to run this workload with a difference kernel.
-    workload.set_parameter("kernel", Resource("arm64-linux-kernel-4.14.134"))
+    workload.set_parameter("kernel",
+        obtain_resource("arm64-linux-kernel-4.14.134")
+    )
 
     # We then set this workload to the board.
     board.set_workload(workload)
@@ -193,8 +195,8 @@ class Workload(AbstractWorkload):
 
         ```python
         board.set_kernel_disk_workload(
-            kernel = Resource("x86-linux-kernel-5.4.49"),
-            disk-image = Resource("x86-ubuntu-18.04-img"),
+            kernel = obtain_resource("x86-linux-kernel-5.4.49"),
+            disk-image = obtain_resource("x86-ubuntu-18.04-img"),
             readfile_contents = "m5_exit; echo 'hello'; m5_exit",
         )
         ```

src/python/gem5/utils/multiprocessing/README.md

@@ -48,8 +48,8 @@ def run_sim(name):
     from gem5.simulate.simulator import Simulator
     board = X86DemoBoard()
     board.set_kernel_disk_workload(
-        kernel=Resource("x86-linux-kernel-5.4.49"),
-        disk_image=Resource("x86-ubuntu-18.04-img"),
+        kernel=obtain_resource("x86-linux-kernel-5.4.49"),
+        disk_image=obtain_resource("x86-ubuntu-18.04-img"),
     )
     simulator = Simulator(board=board)
     simulator.run(max_ticks=10000000)

tests/gem5/configs/arm_boot_exit_run.py

@@ -36,7 +36,7 @@ Characteristics
 from gem5.isas import ISA
 from m5.objects import ArmDefaultRelease
 from gem5.utils.requires import requires
-from gem5.resources.resource import Resource
+from gem5.resources.resource import obtain_resource
 from gem5.simulate.simulator import Simulator
 from m5.objects import VExpress_GEM5_Foundation
 from gem5.coherence_protocol import CoherenceProtocol
@@ -199,15 +199,15 @@ board = ArmBoard(
 
 # Set the Full System workload.
 board.set_kernel_disk_workload(
-    kernel=Resource(
+    kernel=obtain_resource(
         "arm64-linux-kernel-5.4.49",
         resource_directory=args.resource_directory,
     ),
-    bootloader=Resource(
+    bootloader=obtain_resource(
         "arm64-bootloader-foundation",
         resource_directory=args.resource_directory,
     ),
-    disk_image=Resource(
+    disk_image=obtain_resource(
         "arm64-ubuntu-20.04-img",
         resource_directory=args.resource_directory,
     ),

tests/gem5/configs/boot_kvm_fork_run.py

@@ -55,7 +55,7 @@ from gem5.components.processors.cpu_types import (
 from gem5.components.processors.simple_switchable_processor import (
     SimpleSwitchableProcessor,
 )
-from gem5.resources.resource import Resource
+from gem5.resources.resource import obtain_resource
 from gem5.runtime import get_runtime_coherence_protocol
 from gem5.utils.requires import requires
 
@@ -179,10 +179,10 @@ kernel_args = motherboard.get_default_kernel_args() + [args.kernel_args]
 
 # Set the Full System workload.
 motherboard.set_kernel_disk_workload(
-    kernel=Resource(
+    kernel=obtain_resource(
         "x86-linux-kernel-5.4.49", resource_directory=args.resource_directory
     ),
-    disk_image=Resource(
+    disk_image=obtain_resource(
         "x86-ubuntu-18.04-img", resource_directory=args.resource_directory
     ),
     readfile_contents=dedent(

tests/gem5/configs/boot_kvm_switch_exit.py

@@ -45,7 +45,7 @@ from gem5.components.processors.cpu_types import (
 from gem5.components.processors.simple_switchable_processor import (
     SimpleSwitchableProcessor,
 )
-from gem5.resources.resource import Resource
+from gem5.resources.resource import obtain_resource
 from gem5.runtime import get_runtime_coherence_protocol
 from gem5.simulate.simulator import Simulator
 from gem5.simulate.exit_event import ExitEvent
@@ -165,10 +165,10 @@ kernal_args = motherboard.get_default_kernel_args() + [args.kernel_args]
 
 # Set the Full System workload.
 motherboard.set_kernel_disk_workload(
-    kernel=Resource(
+    kernel=obtain_resource(
         "x86-linux-kernel-5.4.49", resource_directory=args.resource_directory
     ),
-    disk_image=Resource(
+    disk_image=obtain_resource(
         "x86-ubuntu-18.04-img", resource_directory=args.resource_directory
     ),
     # The first exit signals to switch processors.

tests/gem5/configs/parsec_disk_run.py

@@ -37,7 +37,7 @@ Notes
 
 import m5.stats
 
-from gem5.resources.resource import Resource
+from gem5.resources.resource import obtain_resource
 from gem5.components.boards.x86_board import X86Board
 from gem5.components.memory import SingleChannelDDR3_1600
 from gem5.components.processors.simple_switchable_processor import (
@@ -205,10 +205,10 @@ command = (
 )
 
 board.set_kernel_disk_workload(
-    kernel=Resource(
+    kernel=obtain_resource(
         "x86-linux-kernel-5.4.49", resource_directory=args.resource_directory
     ),
-    disk_image=Resource(
+    disk_image=obtain_resource(
         "x86-parsec", resource_directory=args.resource_directory
     ),
     readfile_contents=command,

tests/gem5/configs/simple_binary_run.py

@@ -30,7 +30,7 @@ The system has no cache heirarchy and is as "bare-bones" as you can get in
 gem5 while still being functinal.
 """
 
-from gem5.resources.resource import Resource
+from gem5.resources.resource import obtain_resource
 from gem5.components.processors.cpu_types import (
     get_cpu_types_str_set,
     get_cpu_type_from_str,
@@ -135,7 +135,9 @@ motherboard = SimpleBoard(
 )
 
 # Set the workload
-binary = Resource(args.resource, resource_directory=args.resource_directory)
+binary = obtain_resource(
+    args.resource, resource_directory=args.resource_directory
+)
 motherboard.set_se_binary_workload(binary, arguments=args.arguments)
 
 # Run the simulation

tests/gem5/configs/simulator_exit_event_run.py

@@ -45,7 +45,7 @@ By default a generator is passed to define the evit_event. A list of functions
 can also be passed. This is enabled by passing the `--list-format` flag.
 """
 
-from gem5.resources.resource import Resource
+from gem5.resources.resource import obtain_resource
 from gem5.components.memory import SingleChannelDDR3_1600
 from gem5.components.boards.simple_board import SimpleBoard
 from gem5.components.cachehierarchies.classic.no_cache import NoCache
@@ -101,7 +101,7 @@ motherboard = SimpleBoard(
 # Set the workload
 # Note: Here we're using the "x86-m5-exit-repeat" resource. This calls an
 # `m5_exit(0)` command in an infinite while-loop.
-binary = Resource(
+binary = obtain_resource(
     "x86-m5-exit-repeat", resource_directory=args.resource_directory
 )
 motherboard.set_se_binary_workload(binary)

tests/gem5/to_tick/configs/tick-exit.py

@@ -28,7 +28,7 @@
 
 """
 
-from gem5.resources.resource import Resource
+from gem5.resources.resource import obtain_resource
 from gem5.isas import ISA
 from gem5.components.memory import SingleChannelDDR3_1600
 from gem5.components.boards.simple_board import SimpleBoard
@@ -76,7 +76,7 @@ motherboard = SimpleBoard(
 )
 
 # Set the workload
-binary = Resource(
+binary = obtain_resource(
     "x86-hello64-static", resource_directory=args.resource_directory
 )
 motherboard.set_se_binary_workload(binary)

tests/gem5/to_tick/configs/tick-to-max.py

@@ -33,7 +33,7 @@ run before, at, or after the running of `simulator.run`.
 time.
 """
 
-from gem5.resources.resource import Resource
+from gem5.resources.resource import obtain_resource
 from gem5.isas import ISA
 from gem5.components.memory import SingleChannelDDR3_1600
 from gem5.components.boards.simple_board import SimpleBoard
@@ -97,7 +97,7 @@ motherboard = SimpleBoard(
 )
 
 # Set the workload
-binary = Resource(
+binary = obtain_resource(
     "x86-hello64-static", resource_directory=args.resource_directory
 )
 motherboard.set_se_binary_workload(binary)

tests/pyunit/stdlib/resources/pyunit_workload_checks.py

@@ -72,14 +72,14 @@ class CustomWorkloadTestSuite(unittest.TestCase):
         )
 
     def test_get_function_str(self) -> None:
-        # Tests `CustomResource.get_function_str`
+        # Tests `CustomWorkload.get_function_str`
 
         self.assertEqual(
             "set_se_binary_workload", self.custom_workload.get_function_str()
         )
 
     def test_get_parameters(self) -> None:
-        # Tests `CustomResource.get_parameter`
+        # Tests `CustomWorkload.get_parameter`
 
         parameters = self.custom_workload.get_parameters()
         self.assertTrue(isinstance(parameters, Dict))
@@ -95,7 +95,7 @@ class CustomWorkloadTestSuite(unittest.TestCase):
         self.assertEquals(6, parameters["arguments"][1])
 
     def test_add_parameters(self) -> None:
-        # Tests `CustomResource.set_parameter` for the case where we add a new
+        # Tests `CustomWorkload.set_parameter` for the case where we add a new
         # parameter value.
 
         self.custom_workload.set_parameter("test_param", 10)
@@ -109,7 +109,7 @@ class CustomWorkloadTestSuite(unittest.TestCase):
         del self.custom_workload.get_parameters()["test_param"]
 
     def test_override_parameter(self) -> None:
-        # Tests `CustomResource.set_parameter` for the case where we override
+        # Tests `CustomWorkload.set_parameter` for the case where we override
         # a parameter's value.
 
         old_value = self.custom_workload.get_parameters()["binary"]