From 01623fac68d18fd96eaf981798f75e39d75ea260 Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Thu, 20 Jul 2023 23:08:39 -0700 Subject: [PATCH 1/5] stdlib,configs,tests: Remove deprecated Resource classes usage (#102) * stdlib,configs,tests: Remove `Resource` class use This class is deprecated, but was still used in various example configuration scriots and tests. This patch replaces it with the `obtain_resource` function. Change-Id: I0c89bf17783ccaaafc18072aaeefb5d1e207bc55 * configs: Remove `CustomDiskImageResource` use The class is deprecated but was still used in the SPEC example scripts. This patch replaces it with the `DiskImageResource` class. Change-Id: Ie0697fe59a3d737b05eb45ff3bc964f42b0387e0 * configs,tests: Remove `CustomResource` use This class is deprecated but was still used in example scripts and mentioned, incorrectly, in comments in the pyunit tests. This patch removes these. Change-Id: Icb6d02f47a5b72cd58551e5dcd59cc72d6a91a01 * stdlib: Remove '\' in Workload docstring example This example shows how to use the Workload. The backslash is not correct Python and would fail if used in this way. Co-authored-by: Jason Lowe-Power --------- Co-authored-by: Jason Lowe-Power --- configs/example/gem5_library/arm-hello.py | 4 ++-- .../checkpoints/riscv-hello-restore-checkpoint.py | 6 +++--- .../checkpoints/riscv-hello-save-checkpoint.py | 4 ++-- .../gem5_library/dramsys/arm-hello-dramsys.py | 4 ++-- configs/example/gem5_library/power-hello.py | 4 ++-- configs/example/gem5_library/riscv-fs.py | 6 +++--- configs/example/gem5_library/riscvmatched-hello.py | 4 ++-- .../example/gem5_library/x86-gapbs-benchmarks.py | 6 +++--- configs/example/gem5_library/x86-npb-benchmarks.py | 6 +++--- .../example/gem5_library/x86-parsec-benchmarks.py | 6 +++--- .../gem5_library/x86-spec-cpu2006-benchmarks.py | 6 ++---- .../gem5_library/x86-spec-cpu2017-benchmarks.py | 10 ++++------ configs/example/lupv/run_lupv.py | 6 +++--- configs/example/sst/riscv_fs.py | 4 ++-- src/python/gem5/resources/workload.py | 14 ++++++++------ src/python/gem5/utils/multiprocessing/README.md | 4 ++-- tests/gem5/configs/arm_boot_exit_run.py | 8 ++++---- tests/gem5/configs/boot_kvm_fork_run.py | 6 +++--- tests/gem5/configs/boot_kvm_switch_exit.py | 6 +++--- tests/gem5/configs/parsec_disk_run.py | 6 +++--- tests/gem5/configs/simple_binary_run.py | 6 ++++-- tests/gem5/configs/simulator_exit_event_run.py | 4 ++-- tests/gem5/to_tick/configs/tick-exit.py | 4 ++-- tests/gem5/to_tick/configs/tick-to-max.py | 4 ++-- .../stdlib/resources/pyunit_workload_checks.py | 8 ++++---- 25 files changed, 73 insertions(+), 73 deletions(-) diff --git a/configs/example/gem5_library/arm-hello.py b/configs/example/gem5_library/arm-hello.py index b4180f11eb..721d71c2cb 100644 --- a/configs/example/gem5_library/arm-hello.py +++ b/configs/example/gem5_library/arm-hello.py @@ -43,7 +43,7 @@ scons build/ARM/gem5.opt from gem5.isas import ISA from gem5.utils.requires import requires -from gem5.resources.resource import Resource +from gem5.resources.resource import obtain_resource from gem5.components.memory import SingleChannelDDR3_1600 from gem5.components.processors.cpu_types import CPUTypes from gem5.components.boards.simple_board import SimpleBoard @@ -84,7 +84,7 @@ board.set_se_binary_workload( # Any resource specified in this file will be automatically retrieved. # At the time of writing, this file is a WIP and does not contain all # resources. Jira ticket: https://gem5.atlassian.net/browse/GEM5-1096 - Resource("arm-hello64-static") + obtain_resource("arm-hello64-static") ) # Lastly we run the simulation. diff --git a/configs/example/gem5_library/checkpoints/riscv-hello-restore-checkpoint.py b/configs/example/gem5_library/checkpoints/riscv-hello-restore-checkpoint.py index 60a7dd0f59..9f9bf839a6 100644 --- a/configs/example/gem5_library/checkpoints/riscv-hello-restore-checkpoint.py +++ b/configs/example/gem5_library/checkpoints/riscv-hello-restore-checkpoint.py @@ -48,7 +48,7 @@ scons build/RISCV/gem5.opt from gem5.isas import ISA from gem5.utils.requires import requires -from gem5.resources.resource import Resource +from gem5.resources.resource import obtain_resource from gem5.components.memory import SingleChannelDDR3_1600 from gem5.components.processors.cpu_types import CPUTypes from gem5.components.boards.simple_board import SimpleBoard @@ -89,8 +89,8 @@ board = SimpleBoard( # configs/example/gem5_library/checkpoints/riscv-hello-save-checkpoint.py board.set_se_binary_workload( # the workload should be the same as the save-checkpoint script - Resource("riscv-hello"), - checkpoint=Resource("riscv-hello-example-checkpoint-v23"), + obtain_resource("riscv-hello"), + checkpoint=obtain_resource("riscv-hello-example-checkpoint-v23"), ) simulator = Simulator( diff --git a/configs/example/gem5_library/checkpoints/riscv-hello-save-checkpoint.py b/configs/example/gem5_library/checkpoints/riscv-hello-save-checkpoint.py index 439d2054fa..234153a57f 100644 --- a/configs/example/gem5_library/checkpoints/riscv-hello-save-checkpoint.py +++ b/configs/example/gem5_library/checkpoints/riscv-hello-save-checkpoint.py @@ -46,7 +46,7 @@ scons build/RISCV/gem5.opt import argparse from gem5.isas import ISA from gem5.utils.requires import requires -from gem5.resources.resource import Resource +from gem5.resources.resource import obtain_resource from gem5.components.memory import SingleChannelDDR3_1600 from gem5.components.processors.cpu_types import CPUTypes from gem5.components.boards.simple_board import SimpleBoard @@ -101,7 +101,7 @@ board.set_se_binary_workload( # Any resource specified in this file will be automatically retrieved. # At the time of writing, this file is a WIP and does not contain all # resources. Jira ticket: https://gem5.atlassian.net/browse/GEM5-1096 - Resource("riscv-hello") + obtain_resource("riscv-hello") ) # Lastly we run the simulation. diff --git a/configs/example/gem5_library/dramsys/arm-hello-dramsys.py b/configs/example/gem5_library/dramsys/arm-hello-dramsys.py index ae0f51ad40..ae2b4bb5b6 100644 --- a/configs/example/gem5_library/dramsys/arm-hello-dramsys.py +++ b/configs/example/gem5_library/dramsys/arm-hello-dramsys.py @@ -35,7 +35,7 @@ correctly. If this is not done correctly this script will run with error. from gem5.isas import ISA from gem5.utils.requires import requires -from gem5.resources.resource import Resource +from gem5.resources.resource import obtain_resource from gem5.components.memory import DRAMSysDDR3_1600 from gem5.components.processors.cpu_types import CPUTypes from gem5.components.boards.simple_board import SimpleBoard @@ -78,7 +78,7 @@ board.set_se_binary_workload( # Any resource specified in this file will be automatically retrieved. # At the time of writing, this file is a WIP and does not contain all # resources. Jira ticket: https://gem5.atlassian.net/browse/GEM5-1096 - Resource("arm-hello64-static") + obtain_resource("arm-hello64-static") ) # Lastly we run the simulation. diff --git a/configs/example/gem5_library/power-hello.py b/configs/example/gem5_library/power-hello.py index cf31778945..59020643e0 100644 --- a/configs/example/gem5_library/power-hello.py +++ b/configs/example/gem5_library/power-hello.py @@ -43,7 +43,7 @@ scons build/POWER/gem5.opt from gem5.isas import ISA from gem5.utils.requires import requires -from gem5.resources.resource import Resource +from gem5.resources.resource import obtain_resource from gem5.components.memory import SingleChannelDDR4_2400 from gem5.components.processors.cpu_types import CPUTypes from gem5.components.boards.simple_board import SimpleBoard @@ -75,7 +75,7 @@ board = SimpleBoard( cache_hierarchy=cache_hierarchy, ) -board.set_se_binary_workload(Resource("power-hello")) +board.set_se_binary_workload(obtain_resource("power-hello")) # Lastly we run the simulation. simulator = Simulator(board=board) diff --git a/configs/example/gem5_library/riscv-fs.py b/configs/example/gem5_library/riscv-fs.py index e4dce027e3..8a0de6c688 100644 --- a/configs/example/gem5_library/riscv-fs.py +++ b/configs/example/gem5_library/riscv-fs.py @@ -48,7 +48,7 @@ from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierar from gem5.components.processors.cpu_types import CPUTypes from gem5.isas import ISA from gem5.utils.requires import requires -from gem5.resources.resource import Resource +from gem5.resources.resource import obtain_resource from gem5.simulate.simulator import Simulator # Run a check to ensure the right version of gem5 is being used. @@ -79,8 +79,8 @@ board = RiscvBoard( # Set the Full System workload. board.set_kernel_disk_workload( - kernel=Resource("riscv-bootloader-vmlinux-5.10"), - disk_image=Resource("riscv-disk-img"), + kernel=obtain_resource("riscv-bootloader-vmlinux-5.10"), + disk_image=obtain_resource("riscv-disk-img"), ) simulator = Simulator(board=board) diff --git a/configs/example/gem5_library/riscvmatched-hello.py b/configs/example/gem5_library/riscvmatched-hello.py index e7b4cf7128..a11ec39159 100644 --- a/configs/example/gem5_library/riscvmatched-hello.py +++ b/configs/example/gem5_library/riscvmatched-hello.py @@ -37,7 +37,7 @@ scons build/RISCV/gem5.opt ``` """ -from gem5.resources.resource import Resource +from gem5.resources.resource import obtain_resource from gem5.simulate.simulator import Simulator from gem5.prebuilt.riscvmatched.riscvmatched_board import RISCVMatchedBoard from gem5.isas import ISA @@ -49,7 +49,7 @@ requires(isa_required=ISA.RISCV) board = RISCVMatchedBoard() # set the hello world riscv binary as the board workload -board.set_se_binary_workload(Resource("riscv-hello")) +board.set_se_binary_workload(obtain_resource("riscv-hello")) # run the simulation with the RISCV Matched board simulator = Simulator(board=board, full_system=False) diff --git a/configs/example/gem5_library/x86-gapbs-benchmarks.py b/configs/example/gem5_library/x86-gapbs-benchmarks.py index b85ce6e7e8..c20d2ea4cc 100644 --- a/configs/example/gem5_library/x86-gapbs-benchmarks.py +++ b/configs/example/gem5_library/x86-gapbs-benchmarks.py @@ -63,7 +63,7 @@ from gem5.components.processors.simple_switchable_processor import ( from gem5.components.processors.cpu_types import CPUTypes from gem5.isas import ISA from gem5.coherence_protocol import CoherenceProtocol -from gem5.resources.resource import Resource +from gem5.resources.resource import obtain_resource from gem5.simulate.simulator import Simulator from gem5.simulate.exit_event import ExitEvent @@ -203,10 +203,10 @@ board.set_kernel_disk_workload( # The x86 linux kernel will be automatically downloaded to the # `~/.cache/gem5` directory if not already present. # gapbs benchamarks was tested with kernel version 4.19.83 - kernel=Resource("x86-linux-kernel-4.19.83"), + kernel=obtain_resource("x86-linux-kernel-4.19.83"), # The x86-gapbs image will be automatically downloaded to the # `~/.cache/gem5` directory if not already present. - disk_image=Resource("x86-gapbs"), + disk_image=obtain_resource("x86-gapbs"), readfile_contents=command, ) diff --git a/configs/example/gem5_library/x86-npb-benchmarks.py b/configs/example/gem5_library/x86-npb-benchmarks.py index cffba5a294..47a62b9fa5 100644 --- a/configs/example/gem5_library/x86-npb-benchmarks.py +++ b/configs/example/gem5_library/x86-npb-benchmarks.py @@ -60,7 +60,7 @@ from gem5.components.processors.simple_switchable_processor import ( from gem5.components.processors.cpu_types import CPUTypes from gem5.isas import ISA from gem5.coherence_protocol import CoherenceProtocol -from gem5.resources.resource import Resource +from gem5.resources.resource import obtain_resource from gem5.simulate.simulator import Simulator from gem5.simulate.simulator import ExitEvent @@ -204,10 +204,10 @@ board.set_kernel_disk_workload( # The x86 linux kernel will be automatically downloaded to the # `~/.cache/gem5` directory if not already present. # npb benchamarks was tested with kernel version 4.19.83 - kernel=Resource("x86-linux-kernel-4.19.83"), + kernel=obtain_resource("x86-linux-kernel-4.19.83"), # The x86-npb image will be automatically downloaded to the # `~/.cache/gem5` directory if not already present. - disk_image=Resource("x86-npb"), + disk_image=obtain_resource("x86-npb"), readfile_contents=command, ) diff --git a/configs/example/gem5_library/x86-parsec-benchmarks.py b/configs/example/gem5_library/x86-parsec-benchmarks.py index aaffec8edc..15f063be92 100644 --- a/configs/example/gem5_library/x86-parsec-benchmarks.py +++ b/configs/example/gem5_library/x86-parsec-benchmarks.py @@ -59,7 +59,7 @@ from gem5.components.processors.simple_switchable_processor import ( from gem5.components.processors.cpu_types import CPUTypes from gem5.isas import ISA from gem5.coherence_protocol import CoherenceProtocol -from gem5.resources.resource import Resource +from gem5.resources.resource import obtain_resource from gem5.simulate.simulator import Simulator from gem5.simulate.exit_event import ExitEvent @@ -185,10 +185,10 @@ board.set_kernel_disk_workload( # The x86 linux kernel will be automatically downloaded to the # `~/.cache/gem5` directory if not already present. # PARSEC benchamarks were tested with kernel version 4.19.83 - kernel=Resource("x86-linux-kernel-4.19.83"), + kernel=obtain_resource("x86-linux-kernel-4.19.83"), # The x86-parsec image will be automatically downloaded to the # `~/.cache/gem5` directory if not already present. - disk_image=Resource("x86-parsec"), + disk_image=obtain_resource("x86-parsec"), readfile_contents=command, ) diff --git a/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py b/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py index 10d5da0adb..63a7b6b236 100644 --- a/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py +++ b/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py @@ -65,7 +65,7 @@ from gem5.components.processors.simple_switchable_processor import ( from gem5.components.processors.cpu_types import CPUTypes from gem5.isas import ISA from gem5.coherence_protocol import CoherenceProtocol -from gem5.resources.resource import Resource, CustomDiskImageResource +from gem5.resources.resource import Resource, DiskImageResource from gem5.simulate.simulator import Simulator from gem5.simulate.exit_event import ExitEvent @@ -261,9 +261,7 @@ board.set_kernel_disk_workload( # 5.4.49 kernel=Resource("x86-linux-kernel-4.19.83"), # The location of the x86 SPEC CPU 2017 image - disk_image=CustomDiskImageResource( - args.image, root_partition=args.partition - ), + disk_image=DiskImageResource(args.image, root_partition=args.partition), readfile_contents=command, ) diff --git a/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py b/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py index cb5f5d19e3..348c26f1ff 100644 --- a/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py +++ b/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py @@ -63,7 +63,7 @@ from gem5.components.processors.simple_switchable_processor import ( from gem5.components.processors.cpu_types import CPUTypes from gem5.isas import ISA from gem5.coherence_protocol import CoherenceProtocol -from gem5.resources.resource import Resource, CustomDiskImageResource +from gem5.resources.resource import obtain_resource, DiskImageResource from gem5.simulate.simulator import Simulator from gem5.simulate.exit_event import ExitEvent @@ -268,18 +268,16 @@ except FileExistsError: command = f"{args.benchmark} {args.size} {output_dir}" -# For enabling CustomResource, we pass an additional parameter to mount the +# For enabling DiskImageResource, we pass an additional parameter to mount the # correct partition. board.set_kernel_disk_workload( # The x86 linux kernel will be automatically downloaded to the # `~/.cache/gem5` directory if not already present. # SPEC CPU2017 benchamarks were tested with kernel version 4.19.83 - kernel=Resource("x86-linux-kernel-4.19.83"), + kernel=obtain_resource("x86-linux-kernel-4.19.83"), # The location of the x86 SPEC CPU 2017 image - disk_image=CustomDiskImageResource( - args.image, root_partition=args.partition - ), + disk_image=DiskImageResource(args.image, root_partition=args.partition), readfile_contents=command, ) diff --git a/configs/example/lupv/run_lupv.py b/configs/example/lupv/run_lupv.py index d92ea3fa3f..e106d051e7 100644 --- a/configs/example/lupv/run_lupv.py +++ b/configs/example/lupv/run_lupv.py @@ -42,7 +42,7 @@ from gem5.components.processors.simple_processor import SimpleProcessor from gem5.components.processors.cpu_types import CPUTypes from gem5.isas import ISA from gem5.utils.requires import requires -from gem5.resources.resource import Resource, CustomResource +from gem5.resources.resource import obtain_resource import argparse @@ -98,8 +98,8 @@ board = LupvBoard( # Set the Full System workload. board.set_kernel_disk_workload( - kernel=Resource("riscv-lupio-linux-kernel"), - disk_image=Resource("riscv-lupio-busybox-img"), + kernel=obtain_resource("riscv-lupio-linux-kernel"), + disk_image=obtain_resource("riscv-lupio-busybox-img"), ) diff --git a/configs/example/sst/riscv_fs.py b/configs/example/sst/riscv_fs.py index fc8f8618c4..77db9e4dbe 100644 --- a/configs/example/sst/riscv_fs.py +++ b/configs/example/sst/riscv_fs.py @@ -29,7 +29,7 @@ from m5.objects import * from os import path # For downloading the disk image -from gem5.resources.resource import Resource +from gem5.resources.resource import obtain_resource import argparse @@ -139,7 +139,7 @@ cpu_clock_rate = args.cpu_clock_rate memory_size = args.memory_size # Try downloading the Resource -bbl_resource = Resource("riscv-boot-exit-nodisk") +bbl_resource = obtain_resource("riscv-boot-exit-nodisk") bbl_path = bbl_resource.get_local_path() system = System() diff --git a/src/python/gem5/resources/workload.py b/src/python/gem5/resources/workload.py index 0798b891ab..5b25bf879f 100644 --- a/src/python/gem5/resources/workload.py +++ b/src/python/gem5/resources/workload.py @@ -52,7 +52,7 @@ class AbstractWorkload: workload = CustomWorkload( function = "set_se_binary_workload", parameters = { - "binary" : Resource("x86-print-this"), + "binary" : obtain_resource("x86-print-this"), "arguments" : ["hello", 6] }, ) @@ -64,7 +64,7 @@ class AbstractWorkload: ```py board.set_se_binary_workload( - binary = Resource("x86-print-this"), + binary = obtain_resource("x86-print-this"), arguments = ["hello", 6], ) ``` @@ -121,7 +121,7 @@ class CustomWorkload(AbstractWorkload): workload = CustomWorkload( function = "set_se_binary_workload", parameters = { - "binary" : Resource("x86-print-this"), + "binary" : obtain_resource("x86-print-this"), "arguments" : ["hello", 6] }, ) @@ -148,7 +148,9 @@ class Workload(AbstractWorkload): # Optionally we can override a parameter in the workload. In this example # we are going to run this workload with a difference kernel. - workload.set_parameter("kernel", Resource("arm64-linux-kernel-4.14.134")) + workload.set_parameter("kernel", + obtain_resource("arm64-linux-kernel-4.14.134") + ) # We then set this workload to the board. board.set_workload(workload) @@ -193,8 +195,8 @@ class Workload(AbstractWorkload): ```python board.set_kernel_disk_workload( - kernel = Resource("x86-linux-kernel-5.4.49"), - disk-image = Resource("x86-ubuntu-18.04-img"), + kernel = obtain_resource("x86-linux-kernel-5.4.49"), + disk-image = obtain_resource("x86-ubuntu-18.04-img"), readfile_contents = "m5_exit; echo 'hello'; m5_exit", ) ``` diff --git a/src/python/gem5/utils/multiprocessing/README.md b/src/python/gem5/utils/multiprocessing/README.md index da2116c44c..c6b0406e54 100644 --- a/src/python/gem5/utils/multiprocessing/README.md +++ b/src/python/gem5/utils/multiprocessing/README.md @@ -48,8 +48,8 @@ def run_sim(name): from gem5.simulate.simulator import Simulator board = X86DemoBoard() board.set_kernel_disk_workload( - kernel=Resource("x86-linux-kernel-5.4.49"), - disk_image=Resource("x86-ubuntu-18.04-img"), + kernel=obtain_resource("x86-linux-kernel-5.4.49"), + disk_image=obtain_resource("x86-ubuntu-18.04-img"), ) simulator = Simulator(board=board) simulator.run(max_ticks=10000000) diff --git a/tests/gem5/configs/arm_boot_exit_run.py b/tests/gem5/configs/arm_boot_exit_run.py index a8ea6eeea7..ffb41459f5 100644 --- a/tests/gem5/configs/arm_boot_exit_run.py +++ b/tests/gem5/configs/arm_boot_exit_run.py @@ -36,7 +36,7 @@ Characteristics from gem5.isas import ISA from m5.objects import ArmDefaultRelease from gem5.utils.requires import requires -from gem5.resources.resource import Resource +from gem5.resources.resource import obtain_resource from gem5.simulate.simulator import Simulator from m5.objects import VExpress_GEM5_Foundation from gem5.coherence_protocol import CoherenceProtocol @@ -199,15 +199,15 @@ board = ArmBoard( # Set the Full System workload. board.set_kernel_disk_workload( - kernel=Resource( + kernel=obtain_resource( "arm64-linux-kernel-5.4.49", resource_directory=args.resource_directory, ), - bootloader=Resource( + bootloader=obtain_resource( "arm64-bootloader-foundation", resource_directory=args.resource_directory, ), - disk_image=Resource( + disk_image=obtain_resource( "arm64-ubuntu-20.04-img", resource_directory=args.resource_directory, ), diff --git a/tests/gem5/configs/boot_kvm_fork_run.py b/tests/gem5/configs/boot_kvm_fork_run.py index 84e273d842..cb6d1b44e1 100644 --- a/tests/gem5/configs/boot_kvm_fork_run.py +++ b/tests/gem5/configs/boot_kvm_fork_run.py @@ -55,7 +55,7 @@ from gem5.components.processors.cpu_types import ( from gem5.components.processors.simple_switchable_processor import ( SimpleSwitchableProcessor, ) -from gem5.resources.resource import Resource +from gem5.resources.resource import obtain_resource from gem5.runtime import get_runtime_coherence_protocol from gem5.utils.requires import requires @@ -179,10 +179,10 @@ kernel_args = motherboard.get_default_kernel_args() + [args.kernel_args] # Set the Full System workload. motherboard.set_kernel_disk_workload( - kernel=Resource( + kernel=obtain_resource( "x86-linux-kernel-5.4.49", resource_directory=args.resource_directory ), - disk_image=Resource( + disk_image=obtain_resource( "x86-ubuntu-18.04-img", resource_directory=args.resource_directory ), readfile_contents=dedent( diff --git a/tests/gem5/configs/boot_kvm_switch_exit.py b/tests/gem5/configs/boot_kvm_switch_exit.py index 1347e68ba4..2d21261161 100644 --- a/tests/gem5/configs/boot_kvm_switch_exit.py +++ b/tests/gem5/configs/boot_kvm_switch_exit.py @@ -45,7 +45,7 @@ from gem5.components.processors.cpu_types import ( from gem5.components.processors.simple_switchable_processor import ( SimpleSwitchableProcessor, ) -from gem5.resources.resource import Resource +from gem5.resources.resource import obtain_resource from gem5.runtime import get_runtime_coherence_protocol from gem5.simulate.simulator import Simulator from gem5.simulate.exit_event import ExitEvent @@ -165,10 +165,10 @@ kernal_args = motherboard.get_default_kernel_args() + [args.kernel_args] # Set the Full System workload. motherboard.set_kernel_disk_workload( - kernel=Resource( + kernel=obtain_resource( "x86-linux-kernel-5.4.49", resource_directory=args.resource_directory ), - disk_image=Resource( + disk_image=obtain_resource( "x86-ubuntu-18.04-img", resource_directory=args.resource_directory ), # The first exit signals to switch processors. diff --git a/tests/gem5/configs/parsec_disk_run.py b/tests/gem5/configs/parsec_disk_run.py index 5c2fa75f65..a0911d46e3 100644 --- a/tests/gem5/configs/parsec_disk_run.py +++ b/tests/gem5/configs/parsec_disk_run.py @@ -37,7 +37,7 @@ Notes import m5.stats -from gem5.resources.resource import Resource +from gem5.resources.resource import obtain_resource from gem5.components.boards.x86_board import X86Board from gem5.components.memory import SingleChannelDDR3_1600 from gem5.components.processors.simple_switchable_processor import ( @@ -205,10 +205,10 @@ command = ( ) board.set_kernel_disk_workload( - kernel=Resource( + kernel=obtain_resource( "x86-linux-kernel-5.4.49", resource_directory=args.resource_directory ), - disk_image=Resource( + disk_image=obtain_resource( "x86-parsec", resource_directory=args.resource_directory ), readfile_contents=command, diff --git a/tests/gem5/configs/simple_binary_run.py b/tests/gem5/configs/simple_binary_run.py index f5e097eaae..1ad4897415 100644 --- a/tests/gem5/configs/simple_binary_run.py +++ b/tests/gem5/configs/simple_binary_run.py @@ -30,7 +30,7 @@ The system has no cache heirarchy and is as "bare-bones" as you can get in gem5 while still being functinal. """ -from gem5.resources.resource import Resource +from gem5.resources.resource import obtain_resource from gem5.components.processors.cpu_types import ( get_cpu_types_str_set, get_cpu_type_from_str, @@ -135,7 +135,9 @@ motherboard = SimpleBoard( ) # Set the workload -binary = Resource(args.resource, resource_directory=args.resource_directory) +binary = obtain_resource( + args.resource, resource_directory=args.resource_directory +) motherboard.set_se_binary_workload(binary, arguments=args.arguments) # Run the simulation diff --git a/tests/gem5/configs/simulator_exit_event_run.py b/tests/gem5/configs/simulator_exit_event_run.py index f4e8ab9ce8..c34cfe3ec9 100644 --- a/tests/gem5/configs/simulator_exit_event_run.py +++ b/tests/gem5/configs/simulator_exit_event_run.py @@ -45,7 +45,7 @@ By default a generator is passed to define the evit_event. A list of functions can also be passed. This is enabled by passing the `--list-format` flag. """ -from gem5.resources.resource import Resource +from gem5.resources.resource import obtain_resource from gem5.components.memory import SingleChannelDDR3_1600 from gem5.components.boards.simple_board import SimpleBoard from gem5.components.cachehierarchies.classic.no_cache import NoCache @@ -101,7 +101,7 @@ motherboard = SimpleBoard( # Set the workload # Note: Here we're using the "x86-m5-exit-repeat" resource. This calls an # `m5_exit(0)` command in an infinite while-loop. -binary = Resource( +binary = obtain_resource( "x86-m5-exit-repeat", resource_directory=args.resource_directory ) motherboard.set_se_binary_workload(binary) diff --git a/tests/gem5/to_tick/configs/tick-exit.py b/tests/gem5/to_tick/configs/tick-exit.py index 9b412cbfb6..4f13d723fa 100644 --- a/tests/gem5/to_tick/configs/tick-exit.py +++ b/tests/gem5/to_tick/configs/tick-exit.py @@ -28,7 +28,7 @@ """ -from gem5.resources.resource import Resource +from gem5.resources.resource import obtain_resource from gem5.isas import ISA from gem5.components.memory import SingleChannelDDR3_1600 from gem5.components.boards.simple_board import SimpleBoard @@ -76,7 +76,7 @@ motherboard = SimpleBoard( ) # Set the workload -binary = Resource( +binary = obtain_resource( "x86-hello64-static", resource_directory=args.resource_directory ) motherboard.set_se_binary_workload(binary) diff --git a/tests/gem5/to_tick/configs/tick-to-max.py b/tests/gem5/to_tick/configs/tick-to-max.py index 2b679df412..89396915cf 100644 --- a/tests/gem5/to_tick/configs/tick-to-max.py +++ b/tests/gem5/to_tick/configs/tick-to-max.py @@ -33,7 +33,7 @@ run before, at, or after the running of `simulator.run`. time. """ -from gem5.resources.resource import Resource +from gem5.resources.resource import obtain_resource from gem5.isas import ISA from gem5.components.memory import SingleChannelDDR3_1600 from gem5.components.boards.simple_board import SimpleBoard @@ -97,7 +97,7 @@ motherboard = SimpleBoard( ) # Set the workload -binary = Resource( +binary = obtain_resource( "x86-hello64-static", resource_directory=args.resource_directory ) motherboard.set_se_binary_workload(binary) diff --git a/tests/pyunit/stdlib/resources/pyunit_workload_checks.py b/tests/pyunit/stdlib/resources/pyunit_workload_checks.py index b374e7a8d3..ef7c3caba1 100644 --- a/tests/pyunit/stdlib/resources/pyunit_workload_checks.py +++ b/tests/pyunit/stdlib/resources/pyunit_workload_checks.py @@ -72,14 +72,14 @@ class CustomWorkloadTestSuite(unittest.TestCase): ) def test_get_function_str(self) -> None: - # Tests `CustomResource.get_function_str` + # Tests `CustomWorkload.get_function_str` self.assertEqual( "set_se_binary_workload", self.custom_workload.get_function_str() ) def test_get_parameters(self) -> None: - # Tests `CustomResource.get_parameter` + # Tests `CustomWorkload.get_parameter` parameters = self.custom_workload.get_parameters() self.assertTrue(isinstance(parameters, Dict)) @@ -95,7 +95,7 @@ class CustomWorkloadTestSuite(unittest.TestCase): self.assertEquals(6, parameters["arguments"][1]) def test_add_parameters(self) -> None: - # Tests `CustomResource.set_parameter` for the case where we add a new + # Tests `CustomWorkload.set_parameter` for the case where we add a new # parameter value. self.custom_workload.set_parameter("test_param", 10) @@ -109,7 +109,7 @@ class CustomWorkloadTestSuite(unittest.TestCase): del self.custom_workload.get_parameters()["test_param"] def test_override_parameter(self) -> None: - # Tests `CustomResource.set_parameter` for the case where we override + # Tests `CustomWorkload.set_parameter` for the case where we override # a parameter's value. old_value = self.custom_workload.get_parameters()["binary"] From 75b6fa5ad11e93f37a97a9388ddbf2d787457938 Mon Sep 17 00:00:00 2001 From: Gabriel Busnot Date: Fri, 21 Jul 2023 20:11:09 +0200 Subject: [PATCH 2/5] base: Ostream helpers (iterable, tuple, pair, enum, pointers, optional) (#77) * base: Enable stl_helpers::operator<< in _formatString The string format (%s) eventually relies on bare operator<< to display any type T. This gives the opportunity to use the helpers in stl_helpers. This patch enables printing enums, pairs, tuples, vectors, maps and others in a PRINTF debug macro without any extra manual operation. Change-Id: I8ac85133ebadcb95354598c1cfe687d8fffb89e2 * base: Add Printer util class to force use of operator<< helpers Wrapping any value in a Printer instance before using operator<< will force the use of stl_helpers::operator<<. Change-Id: I7b505194eeabc3e0721effd9b5ce98f9e151b807 * base: Fix typo in ostream_helpers.hh Change-Id: I283a5414f3add4f18649b77153dcbcc8661bc81e * base: Disambiguate null optional representation in ostream helper Change-Id: I5b093555688566cc405248d3a448a8f3efa67888 * base: Add unit test for std::optional ostream helper Change-Id: I6fb9ced5e6461de5685638a162b5534e10710e20 * base: Ostream helpers Printer unit test Change-Id: I11db89e85fd40c12bceecb41cadee78b8e871d7b * base: Unit test for ostream helpers for pointers and smart ptr Change-Id: Ifa87e8b69fdd9a4869250ab40311f352e8f54ed9 * base: Coding style fix in ostream_helpers.test.cc Change-Id: I095c7048fad35e63f979aa601bfc8cde65c9077b * base: Test shared_ptr in ostream_helpers.test.cc Change-Id: I553df0614f1dd6eef2061c4dc1794af8c543b78f --------- Co-authored-by: Gabriel Busnot --- src/base/cprintf_formats.hh | 3 ++ src/base/stl_helpers/ostream_helpers.hh | 36 +++++++++++-- src/base/stl_helpers/ostream_helpers.test.cc | 54 +++++++++++++++++++- 3 files changed, 89 insertions(+), 4 deletions(-) diff --git a/src/base/cprintf_formats.hh b/src/base/cprintf_formats.hh index 4a64780c4a..e4c1048e01 100644 --- a/src/base/cprintf_formats.hh +++ b/src/base/cprintf_formats.hh @@ -34,6 +34,8 @@ #include #include +#include "base/stl_helpers.hh" + namespace gem5 { @@ -221,6 +223,7 @@ template static inline void _formatString(std::ostream &out, const T &data, Format &fmt) { + using stl_helpers::operator<<; if (fmt.width > 0) { std::stringstream foo; foo << data; diff --git a/src/base/stl_helpers/ostream_helpers.hh b/src/base/stl_helpers/ostream_helpers.hh index a1c92e1ed1..680d55f23c 100644 --- a/src/base/stl_helpers/ostream_helpers.hh +++ b/src/base/stl_helpers/ostream_helpers.hh @@ -41,6 +41,19 @@ namespace gem5::stl_helpers { +/* + * Wrap any object in a Printer object to force using a opExtract_impl printing + * function. This is not required for types that do not already enable + * operator<< in another namespace. However, to enable the special printing + * function for, e.g., raw pointers, those must be wrapped in a Printer. + */ +template +struct Printer +{ + Printer(const T& value): value{value} {} + const T& value; +}; + namespace opExtract_impl { @@ -51,7 +64,7 @@ namespace opExtract_impl * mechanism is used. The only entry point in the system is through a primary * dispatch function that won't resolve for non-helped types. Then, recursive * calls go through the secondary dispatch interface that sort between helped - * and non-helped types. Helped typed will enter the system back through the + * and non-helped types. Helped types will enter the system back through the * primary dispatch interface while other types will look for operator<< * through regular lookup, especially ADL. */ @@ -106,7 +119,7 @@ opExtractPrimDisp(std::ostream& os, const std::optional& o) if (o) { return opExtractSecDisp(os, *o); } else { - return os << '-'; + return os << "(-)"; } } @@ -128,6 +141,10 @@ opExtractPrimDisp(std::ostream& os, const std::unique_ptr& p) return opExtractPrimDisp(os, p.get()); } +template +std::ostream& +opExtractPrimDisp(std::ostream& os, const Printer& p); + template constexpr bool isOpExtractNativelySupported = false; @@ -166,6 +183,18 @@ opExtractPrimDisp(std::ostream& os, T* p) } } +template +std::ostream& +opExtractPrimDisp(std::ostream& os, const Printer& p) +{ + if constexpr (isOpExtractHelped) { + return opExtractPrimDisp(os, p.value); + } else { + return os << p.value; + } +} + + template std::ostream& opExtractSecDisp(std::ostream& os, const T& v) @@ -179,7 +208,8 @@ opExtractSecDisp(std::ostream& os, const T& v) } // namespace opExtract_impl -// Add "using stl_helpers::operator<<" in the scope where you want to use it. +// use the Printer wrapper or add "using stl_helpers::operator<<" in the scope +// where you want to use that operator<<. template std::enable_if_t, std::ostream&> operator<<(std::ostream& os, const T& v) diff --git a/src/base/stl_helpers/ostream_helpers.test.cc b/src/base/stl_helpers/ostream_helpers.test.cc index 19a1ece27e..84c936f4a8 100644 --- a/src/base/stl_helpers/ostream_helpers.test.cc +++ b/src/base/stl_helpers/ostream_helpers.test.cc @@ -34,9 +34,9 @@ #include "base/stl_helpers/ostream_helpers.hh" -using gem5::stl_helpers::operator<<; TEST(OstreamHelpers, pair) { + using gem5::stl_helpers::operator<<; auto p = std::make_pair(1, 2); std::ostringstream os; os << p; @@ -44,6 +44,7 @@ TEST(OstreamHelpers, pair) { } TEST(OstreamHelpers, tuple) { + using gem5::stl_helpers::operator<<; auto t = std::make_tuple(true, std::make_pair("Hello", std::string_view("World")), '!'); std::ostringstream os; @@ -52,6 +53,7 @@ TEST(OstreamHelpers, tuple) { } TEST(OstreamHelpers, vector) { + using gem5::stl_helpers::operator<<; auto v = std::vector{"abc", "defg", "hijklm", "\n"}; std::ostringstream os; os << v; @@ -59,8 +61,58 @@ TEST(OstreamHelpers, vector) { } TEST(OstreamHelpers, map) { + using gem5::stl_helpers::operator<<; auto m = std::map{{'a', 0}, {'b', 1}, {'c', 2}, {'d', 3}}; std::ostringstream os; os << m; EXPECT_EQ(os.str(), "[ (a, 0), (b, 1), (c, 2), (d, 3), ]"); } + +TEST(OstreamHelpers, optional) { + using gem5::stl_helpers::operator<<; + auto m = std::make_optional(42); + std::ostringstream os; + os << m; + EXPECT_EQ(os.str(), "42"); + os.str(""); + m.reset(); + os << m; + EXPECT_EQ(os.str(), "(-)"); +} + +TEST(OstreamHelpers, printer) { + std::string hello = "Hello"; + std::ostringstream os; + os << hello; + EXPECT_EQ(os.str(), hello); + + std::ostringstream os2; + os2 << gem5::stl_helpers::Printer(hello); + EXPECT_EQ(os2.str(), "[ H, e, l, l, o, ]"); +} + + +TEST(OstreamHelpers, pointers) { + auto helped_representation = [](const auto& val) { + std::ostringstream os; + os << gem5::stl_helpers::Printer(val); + return os.str(); + }; + auto expected_representation = [&](const auto& ptr) { + using gem5::stl_helpers::operator<<; + std::ostringstream os; + auto* raw_ptr = &*ptr; + os << '(' << raw_ptr << ": " << *ptr << ')'; + return os.str(); + }; + + int x = 42; + auto* ptr = &x; + EXPECT_EQ(helped_representation(ptr), expected_representation(ptr)); + + auto uptr = std::make_unique("Hello, World!"); + EXPECT_EQ(helped_representation(uptr), expected_representation(uptr)); + + auto sptr = std::make_shared>(); + EXPECT_EQ(helped_representation(sptr), expected_representation(sptr)); +} From 0dd43346226150330ee3e969b338c31e1e6d21c2 Mon Sep 17 00:00:00 2001 From: Jason Lowe-Power Date: Fri, 21 Jul 2023 12:36:24 -0700 Subject: [PATCH 3/5] misc: Add workflow to close stale issues (#96) Create a new workflow file that will hold jobs that are for managing the repository, issues, prs, etc. This changeset then adds a job to close issues that have been open for 30 days without a response someone marks the issue as "needs details." Change-Id: I23b9b6aa5fa67f205e116c88d5449cb69f53b6f9 Signed-off-by: Jason Lowe-Power --- .github/workflows/utils.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 .github/workflows/utils.yaml diff --git a/.github/workflows/utils.yaml b/.github/workflows/utils.yaml new file mode 100644 index 0000000000..91d0bf1722 --- /dev/null +++ b/.github/workflows/utils.yaml @@ -0,0 +1,19 @@ +# This workflow file contains miscellaneous tasks to manage the repository. +name: Utils for Repository +on: + schedule: + - cron: '30 1 * * *' + workflow_dispatch: + +jobs: + # This job runs the stale action to close issues that have been inactive for 30 days. + # It is scheduled to run every day at 1:30 AM UTC. + close-stale-issues: + runs-on: ubuntu-latest + steps: + - uses: actions/stale@v8.0.0 + with: + close-issue-message: 'This issue is being closed because it has been inactive waiting for response for 30 days. If this is still an issue, please open a new issue and reference this one.' + days-before-stale: 21 + days-before-close: 7 + any-of-labels: 'needs details' From 6a360bd1bba85db4e21afac771ebfb52ccdae0b0 Mon Sep 17 00:00:00 2001 From: Melissa Jost Date: Fri, 21 Jul 2023 15:53:12 -0700 Subject: [PATCH 4/5] misc: Update ci-tests.yaml to always clean runner Adds line to make sure the runners are always cleaned whether or not the previous tests pass Change-Id: I980c0232305999fb3548464ea1b6eaeca7bcdbd6 --- .github/workflows/ci-tests.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/ci-tests.yaml b/.github/workflows/ci-tests.yaml index 5e11903a0f..9894716665 100644 --- a/.github/workflows/ci-tests.yaml +++ b/.github/workflows/ci-tests.yaml @@ -103,6 +103,7 @@ jobs: path: output.zip retention-days: 7 - name: Clean runner + if: success() || failure() run: rm -rf ./* || true rm -rf ./.??* || true From 984499329d5b70c1841c39e545878303b4a5ddd5 Mon Sep 17 00:00:00 2001 From: Daniel Kouchekinia Date: Sun, 23 Jul 2023 13:57:06 -0700 Subject: [PATCH 5/5] mem-ruby,configs: Add GLC Atomic Latency VIPER Parameter (#110) Added a GLC atomic latency parameter (glc-atomic-latency) used when enqueueing response messages regarding atomics directly performed in the TCC. This latency is added in addition to the L2 response latency (TCC_latency). This represents the latency of performing an atomic within the L2. With this change, the TCC response queue will receive enqueues with varying latencies as GLC atomic responses will have this added GLC atomic latency while data responses will not. To accommodate this in light of the queue having strict FIFO ordering (which would be violated here), this change also adds an optional parameter bypassStrictFIFO to the SLICC enqueue function which allows overriding strict FIFO requirements for individual messages on a case-by-case basis. This parameter is only being used in the TCC's atomic response enqueue call. Change-Id: Iabd52cbd2c0cc385c1fb3fe7bcd0cc64bdb40aac --- configs/ruby/GPU_VIPER.py | 4 ++++ src/mem/ruby/network/MessageBuffer.cc | 11 +++++++--- src/mem/ruby/network/MessageBuffer.hh | 6 +++++- src/mem/ruby/protocol/GPU_VIPER-TCC.sm | 3 ++- src/mem/slicc/ast/EnqueueStatementAST.py | 26 +++++++++++++++++++----- src/mem/slicc/parser.py | 8 ++++++-- 6 files changed, 46 insertions(+), 12 deletions(-) diff --git a/configs/ruby/GPU_VIPER.py b/configs/ruby/GPU_VIPER.py index ee8d570498..1e95964a40 100644 --- a/configs/ruby/GPU_VIPER.py +++ b/configs/ruby/GPU_VIPER.py @@ -489,6 +489,9 @@ def define_options(parser): help="Size of the mandatory queue in the GPU scalar " "cache controller", ) + parser.add_argument( + "--glc-atomic-latency", type=int, default=1, help="GLC Atomic Latency" + ) def construct_dirs(options, system, ruby_system, network): @@ -875,6 +878,7 @@ def construct_tccs(options, system, ruby_system, network): tcc_cntrl.create(options, ruby_system, system) tcc_cntrl.l2_request_latency = options.gpu_to_dir_latency tcc_cntrl.l2_response_latency = options.TCC_latency + tcc_cntrl.glc_atomic_latency = options.glc_atomic_latency tcc_cntrl_nodes.append(tcc_cntrl) tcc_cntrl.WB = options.WB_L2 tcc_cntrl.number_of_TBEs = 2560 * options.num_compute_units diff --git a/src/mem/ruby/network/MessageBuffer.cc b/src/mem/ruby/network/MessageBuffer.cc index 9a6500978e..9a4439a538 100644 --- a/src/mem/ruby/network/MessageBuffer.cc +++ b/src/mem/ruby/network/MessageBuffer.cc @@ -62,7 +62,8 @@ MessageBuffer::MessageBuffer(const Params &p) m_max_dequeue_rate(p.max_dequeue_rate), m_dequeues_this_cy(0), m_time_last_time_size_checked(0), m_time_last_time_enqueue(0), m_time_last_time_pop(0), - m_last_arrival_time(0), m_strict_fifo(p.ordered), + m_last_arrival_time(0), m_last_message_strict_fifo_bypassed(false), + m_strict_fifo(p.ordered), m_randomization(p.randomization), m_allow_zero_latency(p.allow_zero_latency), m_routing_priority(p.routing_priority), @@ -214,7 +215,8 @@ random_time() } void -MessageBuffer::enqueue(MsgPtr message, Tick current_time, Tick delta) +MessageBuffer::enqueue(MsgPtr message, Tick current_time, Tick delta, + bool bypassStrictFIFO) { // record current time incase we have a pop that also adjusts my size if (m_time_last_time_enqueue < current_time) { @@ -252,7 +254,8 @@ MessageBuffer::enqueue(MsgPtr message, Tick current_time, Tick delta) // Check the arrival time assert(arrival_time >= current_time); - if (m_strict_fifo) { + if (m_strict_fifo && + !(bypassStrictFIFO || m_last_message_strict_fifo_bypassed)) { if (arrival_time < m_last_arrival_time) { panic("FIFO ordering violated: %s name: %s current time: %d " "delta: %d arrival_time: %d last arrival_time: %d\n", @@ -266,6 +269,8 @@ MessageBuffer::enqueue(MsgPtr message, Tick current_time, Tick delta) m_last_arrival_time = arrival_time; } + m_last_message_strict_fifo_bypassed = bypassStrictFIFO; + // compute the delay cycles and set enqueue time Message* msg_ptr = message.get(); assert(msg_ptr != NULL); diff --git a/src/mem/ruby/network/MessageBuffer.hh b/src/mem/ruby/network/MessageBuffer.hh index 279599340a..03a0454433 100644 --- a/src/mem/ruby/network/MessageBuffer.hh +++ b/src/mem/ruby/network/MessageBuffer.hh @@ -123,7 +123,8 @@ class MessageBuffer : public SimObject const MsgPtr &peekMsgPtr() const { return m_prio_heap.front(); } - void enqueue(MsgPtr message, Tick curTime, Tick delta); + void enqueue(MsgPtr message, Tick curTime, Tick delta, + bool bypassStrictFIFO = false); // Defer enqueueing a message to a later cycle by putting it aside and not // enqueueing it in this cycle @@ -271,6 +272,9 @@ class MessageBuffer : public SimObject uint64_t m_msg_counter; int m_priority_rank; + + bool m_last_message_strict_fifo_bypassed; + const bool m_strict_fifo; const MessageRandomization m_randomization; const bool m_allow_zero_latency; diff --git a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm index a83bee0fa5..31fc484973 100644 --- a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm +++ b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm @@ -36,6 +36,7 @@ machine(MachineType:TCC, "TCC Cache") bool WB; /*is this cache Writeback?*/ Cycles l2_request_latency := 50; Cycles l2_response_latency := 20; + Cycles glc_atomic_latency := 0; // From the TCPs or SQCs MessageBuffer * requestFromTCP, network="From", virtual_network="1", vnet_type="request"; @@ -510,7 +511,7 @@ machine(MachineType:TCC, "TCC Cache") action(ar_sendAtomicResponse, "ar", desc="send Atomic Ack") { peek(coreRequestNetwork_in, CPURequestMsg) { - enqueue(responseToCore_out, ResponseMsg, l2_response_latency) { + enqueue(responseToCore_out, ResponseMsg, l2_response_latency + glc_atomic_latency, true) { out_msg.addr := address; out_msg.Type := CoherenceResponseType:TDSysResp; out_msg.Destination.clear(); diff --git a/src/mem/slicc/ast/EnqueueStatementAST.py b/src/mem/slicc/ast/EnqueueStatementAST.py index 148cc3a223..e9bda61911 100644 --- a/src/mem/slicc/ast/EnqueueStatementAST.py +++ b/src/mem/slicc/ast/EnqueueStatementAST.py @@ -31,12 +31,21 @@ from slicc.symbols import Var class EnqueueStatementAST(StatementAST): - def __init__(self, slicc, queue_name, type_ast, lexpr, statements): + def __init__( + self, + slicc, + queue_name, + type_ast, + lexpr, + bypass_strict_fifo, + statements, + ): super().__init__(slicc) self.queue_name = queue_name self.type_ast = type_ast self.latexpr = lexpr + self.bypass_strict_fifo = bypass_strict_fifo self.statements = statements def __repr__(self): @@ -76,10 +85,17 @@ class EnqueueStatementAST(StatementAST): if self.latexpr != None: ret_type, rcode = self.latexpr.inline(True) - code( - "(${{self.queue_name.var.code}}).enqueue(" - "out_msg, clockEdge(), cyclesToTicks(Cycles($rcode)));" - ) + if self.bypass_strict_fifo != None: + bypass_strict_fifo_code = self.bypass_strict_fifo.inline(False) + code( + "(${{self.queue_name.var.code}}).enqueue(" + "out_msg, clockEdge(), cyclesToTicks(Cycles($rcode)), $bypass_strict_fifo_code);" + ) + else: + code( + "(${{self.queue_name.var.code}}).enqueue(" + "out_msg, clockEdge(), cyclesToTicks(Cycles($rcode)));" + ) else: code( "(${{self.queue_name.var.code}}).enqueue(out_msg, " diff --git a/src/mem/slicc/parser.py b/src/mem/slicc/parser.py index 155eb07f7a..d84eab211c 100644 --- a/src/mem/slicc/parser.py +++ b/src/mem/slicc/parser.py @@ -633,11 +633,15 @@ class SLICC(Grammar): def p_statement__enqueue(self, p): "statement : ENQUEUE '(' var ',' type ')' statements" - p[0] = ast.EnqueueStatementAST(self, p[3], p[5], None, p[7]) + p[0] = ast.EnqueueStatementAST(self, p[3], p[5], None, None, p[7]) def p_statement__enqueue_latency(self, p): "statement : ENQUEUE '(' var ',' type ',' expr ')' statements" - p[0] = ast.EnqueueStatementAST(self, p[3], p[5], p[7], p[9]) + p[0] = ast.EnqueueStatementAST(self, p[3], p[5], p[7], None, p[9]) + + def p_statement__enqueue_latency_bypass_strict_fifo(self, p): + "statement : ENQUEUE '(' var ',' type ',' expr ',' expr ')' statements" + p[0] = ast.EnqueueStatementAST(self, p[3], p[5], p[7], p[9], p[11]) def p_statement__defer_enqueueing(self, p): "statement : DEFER_ENQUEUEING '(' var ',' type ')' statements"