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mem-ruby: Fix of an address bug in MESI_Two_Level-dir.sm

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Physical access address and line address were mixed up in
qw_queueMemoryWBRequest_partial

Change-Id: I0b238ffc59d2bb3de221d96905c75b7616eac964
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67661
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
This commit is contained in:
Gabriel Busnot
2022-10-05 10:49:48 +02:00
committed by Gabriel B.
parent d79941df7a
commit 159953080a
1 changed files with 1 additions and 1 deletions
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src/mem/ruby/protocol/MESI_Two_Level-dir.sm
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@@ -365,7 +365,7 @@ machine(MachineType:Directory, "MESI Two Level directory protocol")
desc="Queue off-chip writeback request") {
peek(requestNetwork_in, RequestMsg) {
enqueue(memQueue_out, MemoryMsg, to_mem_ctrl_latency) {
out_msg.addr := address;
out_msg.addr := in_msg.addr;
out_msg.Type := MemoryRequestType:MEMORY_WB;
out_msg.Sender := machineID;
out_msg.MessageSize := MessageSizeType:Writeback_Data;