Gem5Fixture is used to define a fixture for building the gem5
binary. Most tests are expected to define their own Gem5Fixture,
however, as some might depend on the same binary (e.g.,
./build/ARM/gem5.opt), they will try to re-define a fixture for the
same target. This patchset changes Gem5Fixture to derive from
UniqueFixture.
In addition, this patchset changes the way global fixtures are
discovered to work with the new Gem5Fixture class. Instead of
enumerating them when test definitions are loaded, we do so after the
tests have been filtered according to specified tags (e.g., include
opt variant, exclude fast, debug variants).
Change-Id: Ie868a7e18ef6c3271f3c8a658229657cd43997cb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19251
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
This changeset adds a test to check the redirection features
added in faux-filesystem changeset. The test contains a
"chdir" system call to "/proc" which should be redirected to
"$(gem5-dir)/m5out/fs/proc" (as specified by the config files).
After "chdir", the test subsequently outputs the "/proc/cpuinfo"
file which should output a configuration of a fake cpu with
values set by a Python configuration file.
Note, the test will call "clone" once. To avoid a runtime error,
make sure that you run this test with "-n2" supplied to the
"config/example/se.py" script.
Change-Id: I505b046b7a4feddfa93a6ef0f0773ac43078cc94
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17112
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
The Makefiles for the pthreads test don't behave like typical
Makefiles that support cross compilation. Rewrite the Makefile to make
cross-compilation more convenient and add targets for aarch{32,64}.
Change-Id: I7cae378492681744b6bb11dd5af69db81ec54229
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16022
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Some tests are really just a wrapper around a test script in
configs/. Add a helper method to wrap these scripts to make sure they
are executed in a consistent environment. This wrapper sets up a
global environment that is identical to that created by main() when it
executes the script. Unlike the old wrappers, it updates the module
search path to make relative imports work correctly in Python 3.
Change-Id: Ie9f81ec4e2689aa8cf5ecb9fc8025d3534b5c9ca
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15976
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Most Ruby tests assume that the highest frequency in the system under
test is 1GHz and limits the global tick rate to this frequency. This
assumption is broken since the default Ruby configuration scripts
clock the CPU at 2Ghz, which results in warnings and sometimes
incorrect behaviour.
Change-Id: I4b204660862ce3b0ea4a13df42caacd4398fef8c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15975
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
At Ia49298304f658701ea0800bd79e08db404a655c3 we removed the default
kernel and DTB filenames from FSConfig.py.
However, the regression tests rely on that to find those blobs.
This commit restores those default filenames just for the config of the
regression tests.
Change-Id: I9d7d869b0087ee8a3b63088693f753a703ead5d6
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15957
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
tests/main.py was trying to find paths relative to itself using the
string __name__ (which was __main__) when it should have been using the
string __file__ which holds the name of the file being executed.
Change-Id: I5ff4c42fc7d8b75ff6b96c3cde61baf731d84738
Reviewed-on: https://gem5-review.googlesource.com/c/15675
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
The default python on MacOS doesn’t have an alias to python2.
The official python version supported in gem5 is Python2.7.
This patch updates the shabang according to the version required in gem5.
Change-Id: I9533c0f7858b5b3cab0ef101be1ee5cd718105b0
Reviewed-on: https://gem5-review.googlesource.com/c/15375
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
The AtomicSimpleCPU used to be able to access memory directly to speed
up simulation if no caches are used. This is fine as long as no
switching between CPU models is required. In order to switch to a new
CPU model that requires caches, we currently need to checkpoint the
system and restore it into a new configuration. The new
'atomic_noncaching' memory mode provides a solution that avoids this
issue since caches are bypassed in this mode. This changeset removes
the old fastmem option from the AtomicSimpleCPU and introduces a new
CPU, NonCachingSimpleCPU, which derives from the AtomicSimpleCPU.
The NonCachingSimpleCPU uses the same mechanism as the AtomicSimpleCPU
used to use when accessing memory in when fastmem was enabled.
This changeset also introduces a new switcheroo test that tests
switching between a NonCachingSimpleCPU and a TimingSimpleCPU with
caches.
Change-Id: If01893f9b37528b14f530c11ce6f53c097582c21
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12419
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Add a test to print out stack contents for SE mode programs.
The test will print out argc, argv, envp, and some auxiliary
vectors.
Change-Id: I489d752ee40fde24c531d8918d0c050f4df936c5
Reviewed-on: https://gem5-review.googlesource.com/3440
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
This adds Makefiles for hello for ARM and x86 by leveraging docker and
dockcross. See https://github.com/dockcross/dockcross for more
information.
These Makefiles also allow for automatic uploading to the correct location
for users to download when running the new tests.
Change-Id: I7085000393cd5283502a7af362c85befda749181
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/4883
This patch adds a subset (rv64*) of RISC-V assembly tests. The original
riscv-test project can be found here:
https://github.com/riscv/riscv-tests. The riscv-test project is under the
BSD license (https://github.com/riscv/riscv-tests/blob/master/LICENSE)
and is maintained separately from gem5 project.
The tests have been slightly modified to work in gem5 SE mode:
(1) Removed a trap handler used in riscv-tests for bare-metal systems
(2) Instead of throwing an exception, the tests call the exit syscall
with
the exit code of
- '0' if SUCCESS
- Failed test case's number (non-zero) if FAILURE
The exit code can be captured after a simuation completes.
In addition to original RISC-V assembly tests, this patch adds several
assembly tests specifically for AMO, LR, SC and system calls. Those
tests target a multi-core system.
(1) rv64uamt: multi-threaded tests for A-extension instructions
(2) rv64samt: multi-threaded tests for clone and futex system calls
This patch also makes the style checker ignore RISC-V assembly test
directory. The assembly tests are maintained in an external project
that does not follow the gem5 coding conventions.
Please find more details in the README file included in this patch.
Change-Id: Id1015d9a2c6c7d0341fa8b81483289e5f0bfcec0
Reviewed-on: https://gem5-review.googlesource.com/6703
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
The class re-uses the existing MSHR and write queue. At the moment
every single access is handled by the cache, even uncacheable
accesses, and nothing is forwarded.
This is a modified version of a changeset put together by Andreas
Hansson <andreas.hansson@arm.com>
Change-Id: I41f7f9c2b8c7fa5ec23712a4446e8adb1c9a336a
Reviewed-on: https://gem5-review.googlesource.com/8291
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Prior to this changeset the bootloader rom (instantiated as a
SimpleMemory) in ruby Arm systems was treated as an IO device and it
was fronted by a DMA controller. This changeset moves the bootloader
rom and adds it to the system as another memory with a dedicated
directory controller.
Change-Id: I094fed031cdef7f77a939d94f948d967b349b7e0
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8741
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Simple program that spawns threads equal to the number of CPU cores and
has some false sharing for testing coherence protocols.
Change-Id: I5be907fd6fea9a8b8e80b63785d186619be41354
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8901
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Starting with version 3, scons imposes using the print function instead
of the print statement in code it processes. To get things building
again, this change moves all python code within gem5 to use the
function version. Another change by another author separately made this
same change to the site_tools and site_init.py files.
Change-Id: I2de7dc3b1be756baad6f60574c47c8b7e80ea3b0
Reviewed-on: https://gem5-review.googlesource.com/8761
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
This patch makes use of ImmOp's polymorphism to remove unnecessary
casting from the implementations of arithmetic instructions with
immediate operands and to remove the CUIOp format by combining it with
the CIOp format (compressed arithmetic instructions with immediate
operands). Interestingly, RISC-V specifies that instructions with
unsigned immediate operands still need to sign-extend the immediates
from 12 (or 20) bits to 64 bits, so that is left alone.
Change-Id: If20d70c1e90f379b9ed8a4155b2b9222b6defe16
Reviewed-on: https://gem5-review.googlesource.com/6401
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Tuan Ta <qtt2@cornell.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
This patch adds two regression tests that execute the script in the
configs dir for triggering low power mode transitions. A separate
test is required for each page policy because for close-adaptive
page policy the DRAM goes into the Precharge Power-down mode while
for open-adaptive page policy it goes into the Activate Power-down
mode.
Change-Id: Iad61af23f132db046f2857cc3ef64b2bf42cf5e4
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5726
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
