tests: Convert memtest to new framework

The original memtest is located at:
https://gem5.googlesource.com/public/gem5/+/master/tests/configs/memtest.py

Change-Id: I58be6fb1675f6502d6644d502915df80aa197a4a
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15836
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

tests/gem5/memory/memtest-run.py

@@ -0,0 +1,85 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ron Dreslinski
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../../../configs/')
+from common.Caches import *
+
+#MAX CORES IS 8 with the fals sharing method
+nb_cores = 8
+cpus = [MemTest(max_loads = 1e5, progress_interval = 1e4)
+        for i in xrange(nb_cores) ]
+
+# system simulated
+system = System(cpu = cpus,
+                physmem = SimpleMemory(),
+                membus = SystemXBar())
+# Dummy voltage domain for all our clock domains
+system.voltage_domain = VoltageDomain()
+system.clk_domain = SrcClockDomain(clock = '1GHz',
+                                   voltage_domain = system.voltage_domain)
+
+# Create a seperate clock domain for components that should run at
+# CPUs frequency
+system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
+                                       voltage_domain = system.voltage_domain)
+
+system.toL2Bus = L2XBar(clk_domain = system.cpu_clk_domain)
+system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.master
+
+# connect l2c to membus
+system.l2c.mem_side = system.membus.slave
+
+# add L1 caches
+for cpu in cpus:
+    # All cpus are associated with cpu_clk_domain
+    cpu.clk_domain = system.cpu_clk_domain
+    cpu.l1c = L1Cache(size = '32kB', assoc = 4)
+    cpu.l1c.cpu_side = cpu.port
+    cpu.l1c.mem_side = system.toL2Bus.slave
+
+system.system_port = system.membus.slave
+
+# connect memory to membus
+system.physmem.port = system.membus.master
+
+
+# -----------------------
+# run simulation
+# -----------------------
+
+root = Root( full_system = False, system = system )
+root.system.mem_mode = 'timing'
+
+m5.instantiate()
+exit_event = m5.simulate()
+if exit_event.getCause() != "maximum number of loads reached":
+    exit(1)
+

tests/gem5/memory/simple-run.py

@@ -47,17 +47,14 @@ parser.add_argument('--latency_var', default=None)
 
 args = parser.parse_args()
 
-# both traffic generator and communication monitor are only available
-# if we have protobuf support, so potentially skip this test
-# require_sim_object("TrafficGen")
-# require_sim_object("CommMonitor")
-# This needs to be fixed in the new infrastructure
-
 # even if this is only a traffic generator, call it cpu to make sure
 # the scripts are happy
-cpu = TrafficGen(
-    config_file=os.path.join(os.path.dirname(os.path.abspath(__file__)),
+try:
+    cpu = TrafficGen(
+        config_file=os.path.join(os.path.dirname(os.path.abspath(__file__)),
                              "tgen-simple-mem.cfg"))
+except NameError:
+    m5.fatal("protobuf required for simple memory test")
 
 class MyMem(SimpleMemory):
     if args.bandwidth:
@@ -99,5 +96,5 @@ root.system.mem_mode = 'timing'
 
 m5.instantiate()
 exit_event = m5.simulate(100000000000)
-
-print(exit_event.getCause())
+if exit_event.getCause() != "simulate() limit reached":
+    exit(1)

tests/gem5/memory/test.py

@@ -58,5 +58,12 @@ for name, params in simple_mem_params:
         config=joinpath(getcwd(), 'simple-run.py'),
         config_args = args,
         valid_isas=(constants.null_tag,),
-    )
+        ) # This tests for validity as well as performance
 
+gem5_verify_config(
+    name='memtest',
+    verifiers=(), # No need for verfiers this will return non-zero on fail
+    config=joinpath(getcwd(), 'memtest-run.py'),
+    config_args = [],
+    valid_isas=(constants.null_tag,),
+)