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tests: Update test scripts to work with Python 3

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Change-Id: I71b1e595765fed9e9f234c9722c33ac5348d4f11
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15999
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
This commit is contained in:
Andreas Sandberg
2019-01-28 16:53:47 +00:00
parent d63f735663
commit debb5daace
12 changed files with 22 additions and 18 deletions
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2
tests/configs/base_config.py
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@@ -288,7 +288,7 @@ class BaseFSSystem(BaseSystem):
response_latency = 20,
tgts_per_mshr = 8)
for r in system.mem_ranges]
for i in xrange(len(system.physmem)):
for i in range(len(system.physmem)):
system.physmem[i].port = system.llc[i].mem_side
system.llc[i].cpu_side = system.membus.master

12
tests/configs/gpu-ruby.py
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@@ -197,7 +197,7 @@ if options.TLB_config == "perLane":
# List of compute units; one GPU can have multiple compute units
compute_units = []
for i in xrange(n_cu):
for i in range(n_cu):
compute_units.append(ComputeUnit(cu_id = i, perLaneTLB = per_lane,
num_SIMDs = options.simds_per_cu,
wfSize = options.wf_size,
@@ -227,8 +227,8 @@ for i in xrange(n_cu):
options.ldsBankConflictPenalty)))
wavefronts = []
vrfs = []
for j in xrange(options.simds_per_cu):
for k in xrange(shader.n_wf):
for j in range(options.simds_per_cu):
for k in range(int(shader.n_wf)):
wavefronts.append(Wavefront(simdId = j, wf_slot_id = k))
vrfs.append(VectorRegisterFile(simd_id=j,
num_regs_per_simd=options.vreg_file_size))
@@ -308,15 +308,15 @@ gpu_port_idx = len(system.ruby._cpu_ports) \
gpu_port_idx = gpu_port_idx - options.num_cp * 2
wavefront_size = options.wf_size
for i in xrange(n_cu):
for i in range(n_cu):
# The pipeline issues wavefront_size number of uncoalesced requests
# in one GPU issue cycle. Hence wavefront_size mem ports.
for j in xrange(wavefront_size):
for j in range(wavefront_size):
system.cpu[shader_idx].CUs[i].memory_port[j] = \
system.ruby._cpu_ports[gpu_port_idx].slave[j]
gpu_port_idx += 1
for i in xrange(n_cu):
for i in range(n_cu):
if i > 0 and not i % options.cu_per_sqc:
gpu_port_idx += 1
system.cpu[shader_idx].CUs[i].sqc_port = \

2
tests/configs/memtest-filter.py
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@@ -33,7 +33,7 @@ from common.Caches import *
#MAX CORES IS 8 with the fals sharing method
nb_cores = 8
cpus = [ MemTest() for i in xrange(nb_cores) ]
cpus = [ MemTest() for i in range(nb_cores) ]
# system simulated
system = System(cpu = cpus,

2
tests/configs/memtest-ruby.py
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@@ -66,7 +66,7 @@ nb_cores = 8
# ruby does not support atomic, functional, or uncacheable accesses
cpus = [ MemTest(percent_functional=50,
percent_uncacheable=0, suppress_func_warnings=True) \
for i in xrange(nb_cores) ]
for i in range(nb_cores) ]
# overwrite options.num_cpus with the nb_cores value
options.num_cpus = nb_cores

2
tests/configs/memtest.py
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@@ -33,7 +33,7 @@ from common.Caches import *
#MAX CORES IS 8 with the fals sharing method
nb_cores = 8
cpus = [ MemTest() for i in xrange(nb_cores) ]
cpus = [ MemTest() for i in range(nb_cores) ]
# system simulated
system = System(cpu = cpus,

2
tests/configs/o3-timing-mp-ruby.py
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@@ -30,7 +30,7 @@ import m5
from m5.objects import *
nb_cores = 4
cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
cpus = [ DerivO3CPU(cpu_id=i) for i in range(nb_cores) ]
import ruby_config
ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)

2
tests/configs/pc-simple-timing-ruby.py
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@@ -63,7 +63,7 @@ system.clk_domain = SrcClockDomain(clock = '1GHz',
system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
voltage_domain = system.voltage_domain)
system.cpu = [TimingSimpleCPU(cpu_id=i, clk_domain = system.cpu_clk_domain)
for i in xrange(options.num_cpus)]
for i in range(options.num_cpus)]
Ruby.create_system(options, True, system, system.iobus, system._dma_ports)

2
tests/configs/simple-atomic-mp-ruby.py
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@@ -30,7 +30,7 @@ import m5
from m5.objects import *
nb_cores = 4
cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
cpus = [ AtomicSimpleCPU(cpu_id=i) for i in range(nb_cores) ]
import ruby_config
ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)

2
tests/configs/simple-timing-mp-ruby.py
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@@ -59,7 +59,7 @@ options.l2_assoc=2
options.l3_assoc=2
nb_cores = 4
cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
cpus = [ TimingSimpleCPU(cpu_id=i) for i in range(nb_cores) ]
# overwrite the num_cpus to equal nb_cores
options.num_cpus = nb_cores

2
tests/configs/t1000-simple-atomic.py
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@@ -51,7 +51,7 @@ cpu.connectAllPorts(system.membus)
# the physmem name to avoid bumping all the reference stats
system.physmem = [SimpleMemory(range = r)
for r in system.mem_ranges]
for i in xrange(len(system.physmem)):
for i in range(len(system.physmem)):
system.physmem[i].port = system.membus.master
root = Root(full_system=True, system=system)

2
tests/legacy-configs/run.py
View File

@@ -85,7 +85,7 @@ args = parser.parse_args()
executable = args.executable
for config in args.config:
execfile(config)
exec(compile(open(config).read(), config, 'exec'))
# Initialize all CPUs in a system
def initCPUs(sys):

8
tests/run.py
View File

@@ -209,7 +209,9 @@ test_filename = config
# for ruby configurations, remove the protocol name from the test filename
if re.search('-ruby', test_filename):
test_filename = test_filename.split('-ruby')[0]+'-ruby'
execfile(joinpath(tests_root, 'configs', test_filename + '.py'))
exec(compile( \
open(joinpath(tests_root, 'configs', test_filename + '.py')).read(), \
joinpath(tests_root, 'configs', test_filename + '.py'), 'exec'))
# set default maxtick... script can override
# -1 means run forever
@@ -217,7 +219,9 @@ maxtick = m5.MaxTick
# tweak configuration for specific test
sys.path.append(joinpath(tests_root, category, mode, name))
execfile(joinpath(tests_root, category, mode, name, 'test.py'))
exec(compile( \
open(joinpath(tests_root, category, mode, name, 'test.py')).read(), \
joinpath(tests_root, category, mode, name, 'test.py'), 'exec'))
# Initialize all CPUs in a system
def initCPUs(sys):