tests: add riscv to cpu tests

Change-Id: Id8e767afbb74f79b980d8160eefc13e7f529f1c3
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16889
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
This commit is contained in:
Hoa Nguyen
2019-02-28 18:26:07 -08:00
parent 04bc162f15
commit 6b81e087c2

View File

@@ -38,6 +38,7 @@ workloads = ('Bubblesort','FloatMM')
valid_isas = {
'x86': ('AtomicSimpleCPU', 'TimingSimpleCPU', 'DerivO3CPU'),
'arm': ('AtomicSimpleCPU', 'TimingSimpleCPU', 'MinorCPU', 'DerivO3CPU'),
'riscv': ('AtomicSimpleCPU', 'TimingSimpleCPU', 'MinorCPU', 'DerivO3CPU'),
}