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4319 Commits

Author SHA1 Message Date
Gabe Black
92abe28af4 x86,kvm: Use the new workload event to trigger KVM system calls. 
While events are only used for SE mode for now, this moves to using the
common mechanism and gets rid of the need for the system call specific
pseudo inst.

Change-Id: I53468103d7f046b85cc25cbff94b12dbc946f4f0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34163
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-29 01:35:30 +00:00
Gabe Black
5a2a72bff4 mips: Implement an SE workload for Linux. 
Change-Id: I78f6048cfe06be1b08d54dc7d24cb3518e97be0f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34158
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-29 01:34:55 +00:00
Gabe Black
a78abf07b7 riscv: Implement an SE workload for Linux. 
Change-Id: Ieb7058007e56ce0c8d153c1853e4b92237e98ab8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34156
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-29 01:34:41 +00:00
Gabe Black
24a2f8ffb9 x86,scons: De-indent the main x86 SConscript file. 
Rather than put all the declaration of sources in the body of an "if", if
the "if" wouldn't happen, exit from the SConscript entirely. Then the
other parts of the SConscript can be totally unindented. Also wrap some
lines which were longer than 80 characters.

Change-Id: I113d649cdd051da02d5ab14a4547b26113d2f7ef
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34161
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-28 20:34:45 +00:00
Gabe Black
529e502f05 x86: Separate system call tables into their own files. 
These tables take up a lot of space and obscure what's going on in the
file around them. This change moves them into their own files (one for
32 bit and one for 64 bit). It also moves the x86 local definitions of
some system calls into their own file, and creates a SConscript file for
the linux subdirectory.

Change-Id: Ib0978005783b41789ea59695ad95b0336f6353eb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34160
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-28 20:34:23 +00:00
Gabe Black
81c5ca17be arm: Implement an SE workload for Linux and FreeBSD. 
Change-Id: I3bac27ca8d5ed9fa11b519ea29b73c6d09260157
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34159
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-28 20:34:02 +00:00
Gabe Black
0ab84ea848 arch: Re-add copyrights that were accidentally removed. 
The partial contents of some files were moved into other files, but the
copyright wasn't moved over with them. This propogates the copyright.

Change-Id: I8612e88ffb7584b15924cf747f671ca3cdefbe55
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36716
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-28 20:33:02 +00:00
Giacomo Travaglini
5500400950 arch-x86: Replace any getDTBPtr/getITBPtr usage 
The getMMUPtr should be used instead

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I363c2b50abdd5d2d8442ebf5892eaf17c99c129a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34979
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
 2020-10-27 14:56:39 +00:00
Giacomo Travaglini
18f2e3ab3c arch-sparc: Replace any getDTBPtr/getITBPtr usage 
JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I931b7b4203b9ae18f46e2d985c7c7b5b339cb9e6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34982
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-27 14:56:24 +00:00
Giacomo Travaglini
f28b2e773f arch-riscv: Replace any getDTBPtr/getITBPtr usage 
The getMMUPtr should be used instead

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I46282b43b53b7dc9f9c6bb959d4aa23ee6808a6b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34980
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-27 09:46:08 +00:00
Gabe Black
4eb2360001 sparc: Remove support for Solaris SE mode. 
In SPARC and SE mode, system calls are triggered by a trap exception
with the appropriate trap number, and then a handler within the Workload
(formerly the Process) object recognizes the trap number and triggers
the system call.

For Linux, this special handling happens in the Linux specific Workload,
and other types of traps are passed through to the base SPARC SE
Workload class. For Solaris however, no special handling is implemented.
That means that it's actually impossible for a Solaris SE mode program
to actually trigger a system call, and so while there is some code
written for Solaris SE mode, this feature does not actually work at all.

Also, while it's relatively easy to build binaries for Linux on various
architectures using, for instance, the crosstool-ng configs in util/,
there is no ready made option that I could find for building a SPARC
Solaris cross compiler which would run on x86 linux.

Given that the support that exists isn't actually hooked up properly,
SPARC is not one of the most popular ISAs within gem5, Solaris is not a
widely used operating system, we have (to my knowledge) no test binary
to run, and setting up a cross compiler would be non-trivial, it makes
the most sense to me to remove this support.

Change-Id: I896b5abc4bf337bd4e4c06c49de7111a3b2b784c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33996
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-27 09:18:01 +00:00
Gabe Black
175355f71e sparc: Implement an SE workload for Linux and Solaris. 
I don't have a binary to test Solaris SE mode, but this *should* still
work.

Change-Id: Iaacc2ddd5193d7341bc65b9fdd5657c26d231cf1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33995
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-27 09:17:46 +00:00
Gabe Black
26ed502d4c power: Implement an SE workload for Linux. 
Change-Id: Ie242698b7f9e6ffffd4abdcbb483ee81d64802d9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34157
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Sandipan Das <sandipan@linux.ibm.com>
 2020-10-26 20:32:03 +00:00
Gabe Black
bfad4b77d0 x86: Delegate process loading to the EmuLinux workload. 
This is still triggered by the generic mechanism that tries out all
paths to go from an object file to a process. That's not entirely
necessary since the only loader that should be used when using the
X86ISA::EmuLinux workload is the one it provides, but the rest of gem5
isn't ready for that change yet.

This removes the last lingering reason to keep around the
arch/x86/linux/process.(hh|cc) files, so they have been deleted.

Change-Id: I425b95c9c730f31291790d63bc842e2c0092960d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33904
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-26 20:31:24 +00:00
Gabe Black
f07dbdacfd fastmodel: Fix up for the new standardized create() methods. 
Change-Id: I2e3610b5cad37b67d32907a2c2568b504d5ed113
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36155
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-24 03:35:17 +00:00
Giacomo Travaglini
ad5fa9ebe4 arch-arm: Fix implementation of TLBI ALLEx instructions 
The TLBIALL op in gem5 was designed after the AArch32 TLBIALL instruction.
and was reused by the TLBI ALLEL1, ALLE2, ALLE3 logic.

This is not correct for the following reasons:

- TLBI ALLEx invalidates regardless of the VMID
- TLBI ALLEx (AArch64) is "target regime" oriented, whereas TLBIALL
  (AArch32) is "current regime" oriented

TLBIALL has a different behaviour depending on the current exception
level: if issued at EL1 it will invalidate stage1 translations only; if
at EL2, it will invalidate stage2 translations as well.

TLBI ALLEx is more standard; every TLBI ALLE1 will invalidate stage1 and
stage2 translations. This is because the instruction is not executable
from the guest (EL1)

So for TLBIALL the condition for stage2 forwarding will be:

if (!isStage2 && isHyp) {

Whereas for TLBI ALLEx will be:

if (!isStage2 && target_el == EL1) {

Change-Id: I282f2cfaecbfc883e173770e5d2578b41055bb7a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35241
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-23 16:23:27 +00:00
Giacomo Travaglini
32d88ae46c arch-arm: Rewrite the TLB flushing interface 
We are now using an overloaded flush method which has
different TLBI ops as arguments.

This is simplifying the interface and it is allowing us to
encode some state in the TLBIOp which will then be passed
to the TLB. This is a step towards making the TLB a stateless
cache of translations

Change-Id: Ic4fbae72dc3cfe756047148b1cf5f144298c8b08
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35240
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-23 16:23:27 +00:00
Giacomo Travaglini
2a91ea7586 arch-arm: Reimplement TLB::flushAll 
flushAll is a non architectural flush command; this is not based on
flushAllSecurity anymore. flushAll should always flush stage1 and stage2,
whereas flushAllSecurity is checking for the current state
(vmid, and if we are in Hyp)

Change-Id: I6b81ebfba387e646f256ecbecb7b5ee720745358
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35239
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-23 16:23:27 +00:00
Giacomo Travaglini
1a897957d6 arch-arm: TLBIALL/TLBIASID/TLBIMVA base classes for I/D flavours 
This will be exploited by the incoming patchset

Change-Id: Ic10a8d64910a04d4153b0f2abb133dfd56dbaf62
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35238
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2020-10-23 16:23:27 +00:00
Gabe Black
74005aa8d6 misc: Replace enable_if<>::type with enable_if_t<>. 
This new abreviated form was added for C++14. Now that we're using that
version of the standard, we can move over to it.

Change-Id: Ia291d2b1e73e503c37593b1e1c4c1b3011abc63b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36477
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-23 12:59:59 +00:00
Gabe Black
a79ce29cd6 x86: Move syscall handling for Linux into the EmuLinux workload. 
Change-Id: I3fe1997e62491e9576b787660b7fae5ae99fb5c9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33903
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-22 22:03:55 +00:00
Gabe Black
4e6339acd2 x86: Create an SEWorkload for x86 linux. 
This doesn't do anything interesting yet, but soon it will take over
system call duties from the x86 linux processes.

Change-Id: Ic126fc80def0b458de51d3a9c96120c58e5a75ad
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33902
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-22 22:03:20 +00:00
Gabe Black
7bcef5c048 misc: Fix a few accidental transitive includes. 
Some files depend on definitions from files that they weren't including
themselves. They were working accidentally by getting those definitions
transitively through other, unrelated headers.

Change-Id: I50c919a4eb6c4484d4ee6b7f4fe02f075132964d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36282
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-21 22:56:14 +00:00
Giacomo Travaglini
c1217f4e89 arch: Use getTlb in BaseMMU to reduce boilerplate 
Change-Id: I22dcdf0769e854c252788d415d46da113cb8c60a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35735
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-21 09:47:57 +00:00
Giacomo Travaglini
f6a3e0a2fd arch-arm: Replace any getDTBPtr/getITBPtr usage 
The getMMUPtr should be used instead

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I8f09b0dc9844764fbe1a04b34dd963730c91f531
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34978
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-21 09:33:39 +00:00
Giacomo Travaglini
330a5f7bad misc: BaseCPU using ArchMMU instead of ArchDTB/ArchITB 
With this commit we replace every TLB pointer stored in the
cpu model with a BaseMMU pointer.

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I4932a32f68582b25cd252b5420b54d6a40ee15b8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34976
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-21 09:33:39 +00:00
Jason Lowe-Power
85a36581d4 cpu-kvm, arch-x86: Fix KVM on Intel platforms 
This is the minimal set of changes from the patch that's been floating
around for a few years originally by Mike Upton.

See http://reviews.gem5.org/r/2613/ and
https://gem5-review.googlesource.com/c/public/gem5/+/7361

The change to the tssDesc is the minimal change to get KVM working on
Intel platforms. However, the other changes seem prudent to add.

Tested on both Intel (i7-7700) and AMD (EPYC 7451) platforms.

Change-Id: I000c7ba102ba161c2bb5e224bf826216cf0ff87a
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12278
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-20 16:44:26 +00:00
Gabe Black
215e12b884 misc: Wrap __attribute__((aligned())) in a macro in compiler.hh. 
This attribute is gcc specific (also implemented by clang for
compatibility), and so should be behind a level of abstraction to make
using different compilers easier.

Change-Id: I7495f011f617268dd7a589dc0bcf1b3b7f515046
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35976
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-19 05:52:57 +00:00
Gabe Black
463cb28ca5 misc: Use compiler.hh macros when available. 
Some places were hand coding __attribute__s when macros in compiler.hh
were available to do that job. Using the macros helps abstract away
compiler specific details and should be used when possible.

Change-Id: I94befebcfde2d673e874e9959588f69781bd9021
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35975
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-19 05:52:40 +00:00
Giacomo Travaglini
b3dc64acb9 arch-arm: Implement ArmPMU DTB generation 
This has been implemented by following Linux documentation:

Documentation/devicetree/bindings/arm/pmu.txt

Change-Id: I22583eed3792d5828f9c260e952ec5e8cf9e118b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35476
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2020-10-17 10:21:08 +00:00
Giacomo Travaglini
007f2d9533 dev-arm, fastmodel: Rewrite Gic.interruptCells 
The affinity number (aka PPI partition) is used differently
in GICv2 and GICv3. In GICv2 it is ORed to the triggering type
(3rd cell), whereas it is encoded in the 4th cell in GICv3

Change-Id: I36e45d4ec5fb39befa1a271b531dfed2d8e56c10
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36235
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-17 10:21:08 +00:00
Gabe Black
91d83cc8a1 misc: Standardize the way create() constructs SimObjects. 
The create() method on Params structs usually instantiate SimObjects
using a constructor which takes the Params struct as a parameter
somehow. There has been a lot of needless variation in how that was
done, making it annoying to pass Params down to base classes. Some of
the different forms were:

const Params &
Params &
Params *
const Params *
Params const*

This change goes through and fixes up every constructor and every
create() method to use the const Params & form. We use a reference
because the Params struct should never be null. We use const because
neither the create method nor the consuming object should modify the
record of the parameters as they came in from the config. That would
make consuming them not idempotent, and make it impossible to tell what
the actual simulation configuration was since it would change from any
user visible form (config script, config.ini, dot pdf output).

Change-Id: I77453cba52fdcfd5f4eec92dfb0bddb5a9945f31
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35938
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-14 12:06:44 +00:00
Jordi Vaquero
05e60080dc arch-arm: Implement Armv8.2-LPA 
This is enabled by setting the ArmSystem.phys_addr_range64 to 52.
This will automatically set the ID_AA64MMFR0_EL1.PARange to 0b0110
which encodes the presence of Armv8.2-LPA

Change-Id: If9b36e26cd2a72e55c8e929a632b7b50d909b282
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35956
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-14 06:56:47 +00:00
Jordi Vaquero
e90fb2ca4f arch-arm: Implement Armv8.2-LVA 
Change-Id: I1b489a3629b2376e03e79b158631cb1d0cacc17e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35955
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-14 06:56:47 +00:00
Gabe Black
34c2a5a227 fastmodel: Update to c++14, and add some missing consts. 
During the review for the CortexR52 model, a comment pointed out where
two consts can be added. Also we switched gem5 over to c++14, but the
project files for these other wrappers were still set to c++11.

Change-Id: I5fecdc896b0290deadcd0f55ea1dfe3806a98177
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35857
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-14 00:15:42 +00:00
Gabe Black
7e738c00d2 fastmodel: Add a wrapper for the CortexR52. 
There has been some testing of this wrapper, but some components are
missing. It's not currently possible to read or set Misc registers,
64 bit integer registers, flattened integer registers, or vector
registers. In some cases that's because no mapping from gem5 indexes
to IRIS resource names has been set up, but in some cases, since R52
is 32 bit, no mapping *can* be set up, and we need to figure out what
to do with requests for 64 bit only state.

Change-Id: I2d650a7c1765b39f25058727502c96e6de5aa26b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35635
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-13 12:53:42 +00:00
Gabe Black
14bdba8c66 arch: Use finditer in the (Sub)OperandList classes. 
This method returns an iterator which goes through all the
non-overlapping matches for the given RE, without having to hand code
that same behavior with the more basic "search" method.

Change-Id: I4c4d95cfc8f72125566222aebb56604c3e9e2b03
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35817
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-13 04:57:44 +00:00
Gabe Black
a44460bf3d arch: Pull the (Sub)OperandList classes into their own file. 
Another step in breaking down the isa parser into more manageable parts.

Change-Id: I0c5e70fe481bd17c0069b768129731e99a93ed0d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35816
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-13 04:57:23 +00:00
Gabe Black
86e0cdf824 arch: Minor cleanup of imports in isa_parser.py. 
The with statement and print function are no longer in the future, and
the "inspect" module is not used. Also alphabetize the imports.

Change-Id: I35f2b7b0f7495cb9ca79d2cbe05f020560ec3593
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35280
Reviewed-by: Steve Reinhardt <stever@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-12 04:29:07 +00:00
Gabe Black
2c17978be7 arch: Split utility methods/variables out of the ISA parser. 
Change-Id: Ifbff4bc6633cd11f98b02ba1291a91c3ad189285
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35279
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-12 04:28:50 +00:00
Gabe Black
c05192c669 arch: Split the operand types out of the ISA parser. 
These conceptually go together and don't depend on any other parts of
the parser.

Change-Id: Ia8bff0d0ec210bdeeb080808968faf9528ee03dd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35278
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-12 04:28:37 +00:00
Gabe Black
24a9813ec0 arch: Move the ISA parser into a package. 
This will make splitting the parser into components easier, since it
will keep help keep everything together and organized.

Change-Id: I737641e124b6da8b1b18a49de9110c8424d8cc4f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35277
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-12 04:28:18 +00:00
Gabe Black
af7eddaad1 arch: Build the operand REs in the isa_parser on demand. 
These regular expressions search code snippets to find places where
operands are used. Rather than build them explicitly at the end of
processing the operands{{}} construct, wait until they're first going to
be used. That way, we'll be able to define operands in as many places as
we want, as long as we've done all we're going to do before the first
instructions are defined.

This will pave the way to defining operands in regular python in let
blocks, and then possibly outside of the parser altogether, perhaps into
scons where having lots of output files for individual instructions will
be easier to manage. For now, this just lets you define multiple
operands blocks which is not all that exciting on its own :)

Change-Id: I1179092316c1c0ac2613810bfd236a32235502fb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35237
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Steve Reinhardt <stever@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-09 04:32:00 +00:00
Giacomo Travaglini
79a3091605 arch-arm: Default ArmSystem to AArch64 
Change-Id: I4dad29086c0b3e50bd2011363cb23625811b4b27
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35775
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-08 08:53:11 +00:00
Gabe Black
7cbce53dd8 sparc: Simplify the IntOp format slightly. 
Change-Id: I693e56a04827287712e001cf99620085ab09b8ac
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35236
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-07 23:00:30 +00:00
Gabe Black
cda1221dd4 sparc: Clean up some code in base.isa. 
This includes the filterDoubles function which adds code to combine 32
bit values into doubles or 64 bit values for floating point, and the
splitOutImm function which detects if the code that implements an
instruction has a register and immediate variant, and generates code for
each.

Change-Id: I5524b9acd6e610b51fd91fe70276c34c23be9f85
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35235
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-07 23:00:05 +00:00
Giacomo Travaglini
af8794c378 fastmodel: Add IrisMMU model 
JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: Ida4ec76df5f6192e34a5b3fc6d002c473d48b387
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35415
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-07 10:48:14 +00:00
Giacomo Travaglini
b5d22a80fd arch: Add generic BaseMMU 
This is an abstract class encapsulating the ITB and DTB
(Instruction and Data TLBs)

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I7c8fa2ada319e631564182075da1aaff517ec212
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34975
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-07 10:48:14 +00:00
Hoa Nguyen
e504ce6bc6 arch-arm: Replace call to tmpnam() by a deterministic one 
According to the documentation, the use of tmpnam() should be
avoided.

This commit generates a temporary filename by concat-ing the
object name with an index that is internally tracked, the index
is increased until a filename that is not being used is found.

JIRA: https://gem5.atlassian.net/browse/GEM5-206

Change-Id: Ibfe604d741b6b7d7b02fc051add217f95f81d05e
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35195
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-06 20:07:26 +00:00
Pierre Ayoub
1cdfbde6c2 arch-arm: Add recursion for DTB entry generation inside ArmISA 
In order to generate the ArmPMU's DTB entry, we have to enable recursion
from the ArmISA.

This commit follows this mailing list entry:
https://www.mail-archive.com/gem5-users@gem5.org/msg18401.html

Change-Id: I73012755f0f8c8d4d17278793cf16cb1e8b011df
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35555
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-06 13:56:08 +00:00