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cpu-kvm, arch-x86: Fix KVM on Intel platforms

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This is the minimal set of changes from the patch that's been floating
around for a few years originally by Mike Upton.

See http://reviews.gem5.org/r/2613/ and
https://gem5-review.googlesource.com/c/public/gem5/+/7361

The change to the tssDesc is the minimal change to get KVM working on
Intel platforms. However, the other changes seem prudent to add.

Tested on both Intel (i7-7700) and AMD (EPYC 7451) platforms.

Change-Id: I000c7ba102ba161c2bb5e224bf826216cf0ff87a
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12278
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Jason Lowe-Power
2018-08-28 18:50:21 -07:00
committed by Jason Lowe-Power
parent f612d836fc
commit 85a36581d4
1 changed files with 12 additions and 0 deletions
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12
src/arch/x86/fs_workload.cc
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@@ -189,6 +189,12 @@ FsWorkload::initState()
// 32 bit data segment
SegDescriptor dsDesc = initDesc;
dsDesc.type.e = 0;
dsDesc.type.w = 1;
dsDesc.d = 1;
dsDesc.baseHigh = 0;
dsDesc.baseLow = 0;
uint64_t dsDescVal = dsDesc;
phys_proxy.writeBlob(GDTBase + numGDTEntries * 8, (&dsDescVal), 8);
@@ -204,10 +210,16 @@ FsWorkload::initState()
tc->setMiscReg(MISCREG_SS, (RegVal)ds);
tc->setMiscReg(MISCREG_TSL, 0);
SegAttr ldtAttr = 0;
ldtAttr.unusable = 1;
tc->setMiscReg(MISCREG_TSL_ATTR, ldtAttr);
tc->setMiscReg(MISCREG_TSG_BASE, GDTBase);
tc->setMiscReg(MISCREG_TSG_LIMIT, 8 * numGDTEntries - 1);
SegDescriptor tssDesc = initDesc;
tssDesc.type = 0xB;
tssDesc.s = 0;
uint64_t tssDescVal = tssDesc;
phys_proxy.writeBlob(GDTBase + numGDTEntries * 8, (&tssDescVal), 8);