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arch-arm: TLBIALL/TLBIASID/TLBIMVA base classes for I/D flavours

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This will be exploited by the incoming patchset

Change-Id: Ic10a8d64910a04d4153b0f2abb133dfd56dbaf62
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35238
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
2020-09-18 14:30:09 +01:00
parent 4af84816a4
commit 1a897957d6
1 changed files with 13 additions and 27 deletions
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40
src/arch/arm/tlbi_op.hh
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2019 ARM Limited
* Copyright (c) 2018-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -89,11 +89,11 @@ class TLBIALL : public TLBIOp
};
/** Instruction TLB Invalidate All */
class ITLBIALL : public TLBIOp
class ITLBIALL : public TLBIALL
{
public:
ITLBIALL(ExceptionLevel _targetEL, bool _secure)
: TLBIOp(_targetEL, _secure)
: TLBIALL(_targetEL, _secure)
{}
void broadcast(ThreadContext *tc) = delete;
@@ -102,11 +102,11 @@ class ITLBIALL : public TLBIOp
};
/** Data TLB Invalidate All */
class DTLBIALL : public TLBIOp
class DTLBIALL : public TLBIALL
{
public:
DTLBIALL(ExceptionLevel _targetEL, bool _secure)
: TLBIOp(_targetEL, _secure)
: TLBIALL(_targetEL, _secure)
{}
void broadcast(ThreadContext *tc) = delete;
@@ -129,35 +129,29 @@ class TLBIASID : public TLBIOp
};
/** Instruction TLB Invalidate by ASID match */
class ITLBIASID : public TLBIOp
class ITLBIASID : public TLBIASID
{
public:
ITLBIASID(ExceptionLevel _targetEL, bool _secure, uint16_t _asid)
: TLBIOp(_targetEL, _secure), asid(_asid)
: TLBIASID(_targetEL, _secure, _asid)
{}
void broadcast(ThreadContext *tc) = delete;
void operator()(ThreadContext* tc) override;
protected:
uint16_t asid;
};
/** Data TLB Invalidate by ASID match */
class DTLBIASID : public TLBIOp
class DTLBIASID : public TLBIASID
{
public:
DTLBIASID(ExceptionLevel _targetEL, bool _secure, uint16_t _asid)
: TLBIOp(_targetEL, _secure), asid(_asid)
: TLBIASID(_targetEL, _secure, _asid)
{}
void broadcast(ThreadContext *tc) = delete;
void operator()(ThreadContext* tc) override;
protected:
uint16_t asid;
};
/** TLB Invalidate All, Non-Secure */
@@ -203,39 +197,31 @@ class TLBIMVA : public TLBIOp
};
/** Instruction TLB Invalidate by VA */
class ITLBIMVA : public TLBIOp
class ITLBIMVA : public TLBIMVA
{
public:
ITLBIMVA(ExceptionLevel _targetEL, bool _secure,
Addr _addr, uint16_t _asid)
: TLBIOp(_targetEL, _secure), addr(_addr), asid(_asid)
: TLBIMVA(_targetEL, _secure, _addr, _asid)
{}
void broadcast(ThreadContext *tc) = delete;
void operator()(ThreadContext* tc) override;
protected:
Addr addr;
uint16_t asid;
};
/** Data TLB Invalidate by VA */
class DTLBIMVA : public TLBIOp
class DTLBIMVA : public TLBIMVA
{
public:
DTLBIMVA(ExceptionLevel _targetEL, bool _secure,
Addr _addr, uint16_t _asid)
: TLBIOp(_targetEL, _secure), addr(_addr), asid(_asid)
: TLBIMVA(_targetEL, _secure, _addr, _asid)
{}
void broadcast(ThreadContext *tc) = delete;
void operator()(ThreadContext* tc) override;
protected:
Addr addr;
uint16_t asid;
};
/** TLB Invalidate by Intermediate Physical Address */