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5256 Commits

Author SHA1 Message Date
Gabe Black
7f61db0f2e arch-arm: Switch from (set|read)Vec* to (get|set)Reg* accessors. 
Change-Id: I9e9b51b965402b3c8c94cce1593d62aa2118cd0c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49766
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-08 20:34:19 +00:00
Gabe Black
8f180369fd arch-arm: Rework the condition code regs. 
Change-Id: I0cfaaecb4da27cecc3dc6464b094fe2cf03b407a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49765
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
 2022-06-08 20:34:01 +00:00
Gabe Black
5efe4d4a3a arch-arm: Rework the int regs. 
Change-Id: I352e12d4742f0771859bdbf9634ac87e2c153427
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49764
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
 2022-06-08 20:33:42 +00:00
Gabe Black
7e6fd8423e arch-x86: Rework float regs for getReg and setReg. 
Change-Id: I9ef7493225678923964721bf91f2fd2c43d4d1e7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49760
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
 2022-06-08 07:09:32 +00:00
Gabe Black
d40bedc019 arch-x86: Rework CCRegs for getReg, setReg. 
Put them in a namespace, make them match the style guide, turn them into
RegIds, and replace readCCReg and setCCReg with getReg and setReg.

Change-Id: I46f766a544696caf3dcfc6b34b50f02b86766da4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49759
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-08 07:09:18 +00:00
Gabe Black
84ae0afa59 arch-x86: Put misc reg indexes into a name space. 
Also make them match the style guide.

Change-Id: I845f141f85d4499a5acf56c2161240764906a232
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49758
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
 2022-06-08 07:09:05 +00:00
Gabe Black
c4ea43f462 arch-x86: De-indent arch/x86/regs/misc.hh. 
Namespaces are not supposed to increase indentation.

Change-Id: I6736c5049ea8d853dc67f319192b9eaa97d27cb1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49757
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-08 07:08:50 +00:00
Gabe Black
88143c940b arch-x86: Convert segment indices to fit the style guide. 
Capitalize only their first letter, and use a namespace to namespace
them instead of a SEGMENT_REG_ prefix.

Change-Id: I69778c8d052ad6cc0ffd9e74dd1c643e9d28048d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49756
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
 2022-06-08 07:08:37 +00:00
Gabe Black
b836e6a495 arch-x86: Stop using (read|set)IntReg. 
These accessors just translate a RegIndex x into a RegId(IntRegClass, x)
and then does (get|set)Reg. Instead, we can just do (get|set)Reg
directly, since all the integer register named constants are just RegIds
now.

Change-Id: I9e7551ed66a6979e83c745f2891c452ded1eff0e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49755
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-08 07:08:23 +00:00
Gabe Black
16f7b17fc5 arch-x86: Convert the int register constants from RegIndex to RegId. 
This will let them be used in APIs which expect either, and will help
transition between the two.

Change-Id: I73fc9e55418ad3ab9e08406f0928aa4b1ef30a49
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49754
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-08 07:08:10 +00:00
Gabe Black
9b2328d637 arch-x86: Use a namespace for integer registers. 
Also reformat the integer register index constants to fit with the style
guide, ie remove the INTREG_ prefix (replaced by the namespace) and
captialize only the first letter.

Change-Id: I682a337944f64a1b96b971a1beb895289b9d299e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49752
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-08 07:07:44 +00:00
Gabe Black
a52f92dccb arch: Remove plumbing for an op_idx value in ISA operands. 
Now that op_idx is trivial to calculate (just src_reg_idx or
dest_reg_idx), there's no need to have the indirection and extra
mechanism to funnel a precalculated value around.

Change-Id: I37daeb646b85e050c4b832af28d054ecc3c338b1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49750
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
 2022-06-08 07:07:35 +00:00
Gabe Black
a1b439f91c arch: Remove plumbing for operand predication. 
The operand predication mechanism has been replaced by mapping
predicate-false register reads/writes to InvalidRegClass.

Change-Id: I57e7aadb7a0d682c225f6a5fe673cba8ddf1c4f8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49749
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-08 07:07:15 +00:00
Gabe Black
7216ff214f arch-x86: Turn predicate-false CC regs into InvalidRegClass. 
This makes the (somewhat faulty) predicated register mechanism
unnecessary.

Change-Id: Id053760defd6ac9aaec95c165df5403e7fcb354f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49748
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-08 07:07:02 +00:00
Earl Ou
0260fe7da9 fastmodel: follow .sgproj SIMGEN_COMMAND_LINE 
ARM's .sgproj has SIMGEN_COMMAND_LINE to be fed into simgen when
running. However, simgen itself doesn't parse that option and apply. We
need to parse it by ourself and pass the arg to simgen when invoking.

Change-Id: I43b131a1ca9f98891ab390de583589a710e7c812
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60369
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-08 00:30:16 +00:00
Gabe Black
851c86af6d arch: Improve the regular expression that finds operands. 
This regular expression currently has a negative lookbehind assertion
that the operand name isn't preceded by any numbers or letters. Expand
that to also include the : character, since no operand should have a
namespace specifier in front of it.

Change-Id: I0bd84b69b9dad278191831d82db762ae75ce4bf1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49751
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-07 19:00:12 +00:00
Gabe Black
a40950a5c9 arch,cpu: Remove the idea of a zero register. 
This is now handled by using the InvalidRegClass.

Change-Id: If43d8f27cfebc249ec6600847bcfd98c9e94cf40
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49746
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-07 18:26:33 +00:00
Gabe Black
caffb4e1ff arch: Detect and convert zero registers to InvalidRegClass. 
Change-Id: Ic5e070d303bf05ed1640b441e498d879764b8778
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49745
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-07 18:26:22 +00:00
Gabe Black
8d11bc31b5 arch-arm: Fix dangling pointer to unnamed temporary in nativetrace.cc. 
Name the temporary.

Change-Id: I51d0eaa4a6759c3f288b4215db880af6135e9107
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60409
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-07 06:37:04 +00:00
Hoa Nguyen
373cc39a92 arch-arm: Improve error message when KVM failed to be initialized 
Change-Id: If7f87cbd6c4e01134b17875e7c69f6147a5ed1f6
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60312
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
 2022-06-06 18:17:37 +00:00
Hoa Nguyen
bf71a17982 arch-arm: Add several 64-bit syscalls name to se_workload.cc 
The names are gathered from [1].

This change also makes syscall 293 (rseq) does nothing
instead of raising an error.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/include/uapi/asm-generic/unistd.h?h=v5.15.44.

Change-Id: Ie0a7221db1cc308316fc0a500c454a23bf6029fd
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60229
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
 2022-06-01 18:31:14 +00:00
Hoa Nguyen
96870d4713 arch-riscv: Fix compilation error due to getdents* syscalls 
In src/sim/syscall_emul.*, getdents and getdents64 are guarded
by #ifdefs. Similar #ifdefs should be in se_workload.cc for each
arch.

Change-Id: Ie636a739235711c3e6d8256fd7929b7d8b4ec953
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60189
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-01 18:31:14 +00:00
ksco
53009f9e69 arch-riscv: Add Zfh extension 
This commit adds RISC-V Zfh 1.0 (half-precision IEEE 754 binary16 floating
point) extension to gem5. Include the following commands:

* FLH / FSH
* FMADD.H / FMSUB.H / FNMSUB.H / FNMADD.H
* FADD.H / FSUB.H / FMUL.H / FDIV.H
* FSQRT.H
* FSGNJ.H / FSGNJN.H / FSGNJX.H
* FMIN.H / FMAX.H
* FCVT.S.H / FCVT.H.S
* FCVT.D.H / FCVT.H.D
* FCVT.W.H / FCVT.H.W
* FCVT.WU.H / FCVT.H.WU
* FMV.X.H / FMV.H.X
* FEQ.H / FLT.H / FLE.H
* FCLASS.H
* FCVT.L.H / FCVT.H.L
* FCVT.LU.H / FCVT.H.LU

Change-Id: Id7870fdfa1aa8b840706c3ba2cab8eeaf008880f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60029
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-05-27 01:22:31 +00:00
Bobby R. Bruce
ed6c57e4ab tests,arch-arm: Add guards for ARM-specific test 
The nightly tests, https://jenkins.gem5.org/job/nightly/219/, were
failing with the following error when running build/NULL/unittests.opt:

```
[ENUMDECL] m5.objects.ArmSystem, ArmExtension -> NULL/enums/ArmExtension.hh
terminate called after throwing an instance of 'pybind11::error_already_set'
  what():  ModuleNotFoundError: No module named 'm5.objects.ArmSystem'
At:
  <frozen importlib._bootstrap>(973): _find_and_load_unlocked
  <frozen importlib._bootstrap>(991): _find_and_load
  <frozen importlib._bootstrap>(1014): _gcd_import
  /usr/lib/python3.8/importlib/__init__.py(127): import_module
  build_tools/enum_hh.py(58): <module>
Aborted (core dumped)
scons: *** [build/NULL/enums/ArmExtension.hh] Error 134
```

The reason for this is the 'aapcs64.test' now transitively includes the
'ArmExtension' enum via this commit:
https://gem5-review.googlesource.com/c/public/gem5/+/59471.

As this test now only works with the ARM ISA, a guard has been included.
As noted in the comment, GTest does not have the 'tags' parameter so the
'TARGET_ISA' environment variable was used. This will need updated when
the multi-isa code is incorporated.

Change-Id: I2793094bf7c813afd97933750332fa3f3b7bd8dd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59569
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
 2022-05-11 19:27:33 +00:00
Giacomo Travaglini
1455ac0e0c arch-arm: Turn on EL2/EL3 support by default in ArmSystem 
In order to turn them off a user needs to explicitly do so
by providing a different ArmRelease objec

Change-Id: I227cee80c5517cdd50cf07c62d9a131ce261310f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51011
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-05-11 13:00:42 +00:00
Gabe Black
67f1ec7f5b fastmodel: Make ArmFastModelComponent-s take a tags parameter. 
ArmFastModelComponents must *minimally* be guarded by "arm fastmodel"
tags, but may actually be covered by a more specific tag which is a
subset of "arm fastmodel", for instance if they are controlled by a
kconfig variable and may or may not be included in "gem5 lib"
independently of other sources which are part of "arm fastmodel".

The contents set up by ArmFastModelComponent are already guarded by a
fixed tag, so this change just needs to plumb through the tag as
specified when the ArmFastModelComponent is created instead.

Change-Id: I619c31107acda378a5439718e32938843f024e74
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59473
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
 2022-05-09 20:05:32 +00:00
Giacomo Travaglini
fd250dbed3 arch-arm: Consolidate Arm FEAT check into single hasExtension 
There's no need to have a per extension helper function now
that we rely on ArmExtension objects

We are therefore removing:

* HavePACExt
* HaveLVA
* HaveSecureEL2Ext
* HaveVirtHostExt

Change-Id: I2094c1eb6310506787e5628aa62d0b14e917ab5e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59471
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-05-09 16:45:58 +00:00
Giacomo Travaglini
6412be29f4 arch-arm: Check implemented features through the release object 
This is faster than going through the ISA and reading the corresponding
ID register value

Change-Id: Iec247167f3b99dcabf2908fceb0c2365c37ba017
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59470
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2022-05-09 16:45:58 +00:00
Giacomo Travaglini
20e1ade7ed arch-arm: Do not read SCR on the critical path 
Change-Id: I0318563382b3c910c599f9fa16ad29553129c537
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59469
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-05-09 16:45:58 +00:00
Angie Lee
a8e8d64e5d fastmodel: Fix an index parsing bug on PL330::gem5_getPort 
Change-Id: I2cf1abb0eb21c6bd65f81628be52650ef9250fbb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59369
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-05-09 08:47:45 +00:00
Giacomo Travaglini
7580e8d53d arch-arm: Memoize computeAddrTop in the MMU code 
Profiling gem5 has indicated computeAddrTop as one of the main
contributors in AArch64 simulation time

The utility function gets used in the critical path of gem5, which is
the memory translation subsystem. The function is supposed to compute a
rather trivial task: identifying the "real" most significant bit of a
virtual address.

This turns out to be quite expensive. Why?

The main issue is the AArch32/AArch64 check, which uses the ELIs32
helper. This performs a sequential read of several MiscReg
values until it confirms that an EL is indeed using AArch32 (or
AArch64).

This is functionally accurate but it is too expensive for the critical
path of a program.

This patch is addressing the issue by adding a Memoizer object for the
computeAddrTop function to the CachedState data structure, which is
already holding cached system register values for performance reasons.
Whenever we need to invalidate those sys reg values because of a change
in the translation system, we also flush/invalidate the memoizer cache

Change-Id: If42e945c650c293ace304fb4c35e709783bb82d4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59151
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-05-04 14:04:56 +00:00
Hoa Nguyen
46266596ff arch-arm,cpu: Move KVM_CAP_ARM_IRQ_LINE_LAYOUT_2 check to Kvm 
This change [1] requires performing KVM_CAP_ARM_IRQ_LINE_LAYOUT_2 check.
However, checkExtension() is only available within the Kvm class and
the KvmVM class.

A new function, Kvm::capIRQLineLayout2(), is added for checking the
status of KVM_CAP_ARM_IRQ_LINE_LAYOUT_2.

This fixes a compilation error on Arm systems.

[1] https://gem5-review.googlesource.com/c/public/gem5/+/55964

Change-Id: Ia190e06ab451e0ff8d1c4833cd23b7de8852c6dd
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59310
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
 2022-05-03 17:09:05 +00:00
Hoa Nguyen
2938119f97 arch-arm: Fix GenericTimer param name in BaseArmKvmCPU 
Per change [1], the new name for `int_virt` is `int_el1_virt`.

[1] https://gem5-review.googlesource.com/c/public/gem5/+/58109

Change-Id: Idde4ac831c7a323b80272642e6a48b1c5e488135
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59309
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
 2022-05-03 17:09:05 +00:00
Giacomo Travaglini
9c9b3a5e3d arch-arm: Split purifyTaggedAddr in two sub-functions 
This patch is splitting the purifyTaggedAddr helper in two
by introducing the maskTaggedAddress utility

* The first part computes the top bit of the address (computeAddrTop)
(This is required as the MSBs of a VA could be used to store
tags like in FEAT_Pauth)

* The second part applies some masking to the supplied
address (maskTaggedAddress) depending on the top bit to
purify the VA from the TAG

The motivation of this split will be clear in the next patch:
we want to memoize the expensive computeAddrTop. Memoizing
purifyTaggedAddr is inefficient as the first argument
is the VA of the memory request so multiple memory requests
will allocate multiple entries in the results cache and
memoization will rarely be used.

We will memoize the VA agnostic computeAddrTop instead

Change-Id: Ib3d8bb521be67a1f21c0891e753396299adf500b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59150
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
 2022-05-03 10:40:19 +00:00
Giacomo Travaglini
287bea8a4d arch-arm: PAuth inst disassembled with a capitalized first letter 
This is not aligned with what we do for other Arm instructions.
This patch removes capitalization of the first letter:

Example

Xpaclri -> xpaclri

Change-Id: I04b3d3b386e34e1dceec940af7c43fc42f538722
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59229
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
 2022-04-29 09:15:46 +00:00
Giacomo Travaglini
f8589a4719 sim, arch-riscv: Remove Fault debug flag 
There is already a Faults debug flag used by Arm and X86 so
having both Fault and Faults is highly confusing

Change-Id: Id5c17f19b51c6257dfc470d07ba050a9de7a9db3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59152
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
 2022-04-28 08:52:49 +00:00
Yu-hsin Wang
9e4c5537a4 fastmodel: Add CortexR52 model reset port 
The model reset is an aggregated logic to reset the whole model. The
port helps us to simulate the reboot process.

Change-Id: I15101bfe11dee40b63cc29c2befb610beb3d32aa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58813
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-26 06:31:51 +00:00
Yu-hsin Wang
b4d924fdca fastmodel: Add CortexA76 model reset port 
The model reset is an aggregated logic to reset the whole model. The
port helps us to simulate the reboot process.

Change-Id: I9aacc398b299e26e4675f7229db1afc8f6c8a34f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58814
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-26 06:31:51 +00:00
zhongchengyong
29a39d9472 arch-riscv: RISCV call/ret instructions aren't decoded correctly 
This change adds IsReturn and IsCall flag for RISC-V jump instructions
by define new "JumpConstructor" in standard.isa, and fixes target
overwriting in buildRetPC.

See RAS presentation in spec:
Section 2.5 Page 22 of https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf
Or:
https://github.com/riscv/riscv-isa-manual/blob/master/src/rv32.tex#:~:text=Return%2Daddress%20prediction,%5Cend%7Btable%7D

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1139

Change-Id: I9728757c9f3f81bd498a0ba04664a003dbded3bf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58209
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-21 06:34:40 +00:00
Jerin Joy
70fd98e807 arch-riscv: Added the Zbs bitmanip instructions 
Added the bclr, bclri, bext, bexti, binv, binvi, bset, bseti
instructions.

Changes based on spec:
https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0.pdf

Change-Id: I126d659d973b250b642bd56b3b149f0ee6a3323e
Signed-off-by: Jerin Joy <joy@rivosinc.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58632
Reviewed-by: Luming Wang <wlm199558@126.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
 2022-04-13 20:09:59 +00:00
Jerin Joy
df886bc8c1 arch-riscv: Added the Zbc bitmanip instructions 
Added clmul, clmulh, clmulr instructions.

Changes based on spec:
https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0.pdf

Change-Id: I98dc76ddde052f56e32eabed12af87039def665b
Signed-off-by: Jerin Joy <joy@rivosinc.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58631
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Luming Wang <wlm199558@126.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-13 20:09:59 +00:00
Jerin Joy
aee1622a6c arch-riscv: Added the Zba and Zbb bitmanip instructions 
Zba instructions added:
add.uw, sh1add, sh1add.uw, sh2add, sh2add.uw, sh3add, sh3add.uw, slli.uw

Zbb instructions added:
andn, orn, xnor, clz, clzw, ctz, ctzw, cpop, cpopw, max, maxu, min,
minu, sext.b, sext.h, zext.h, rol, rolw, ror, rori, roriw, rorw, orc.b, rev8

Changes based on spec:
https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0.pdf

Change-Id: I056719f62eee89e0f085d1bf1fa182f9dfe614d8
Signed-off-by: Jerin Joy <joy@rivosinc.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58630
Reviewed-by: Luming Wang <wlm199558@126.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-13 20:09:59 +00:00
Yu-hsin Wang
72255064d6 fastmodel: Export more CortexR52 reset pin 
Change-Id: I20f34ae2061e886b35fe9439dbb8e25ce3571e4f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58811
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-13 08:44:03 +00:00
Yu-hsin Wang
9dce95844a fastmodel: Export more CortexA76 reset pin 
Change-Id: I386cf659fa77b2005f808fde51ef772ac0a57735
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58812
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-13 08:44:03 +00:00
Gabe Black
7392cd470e scons: Ensure the fast model license count is always at least 1. 
Even though the default value for the license count is 1, it seems that
if fast model is disabled, kconfig will set it to 0. When creating a
cycle using itertools over a list with zero elements, it will raise a
StopIteration.

Even though we don't actually try to build any fast model components
in that case, we do still set them up with a license slot. If the
cycle iterator is essentially broken, that will prevent that from
working and break the build.

This change forces the license count to be at least 1, even if fast
model is disabled and the license count may be set to 0 in the config.

Change-Id: Ia8df256a8f292deb6fb6fa3c5f9a7d58c2b7f782
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58490
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-13 02:16:13 +00:00
Gabe Black
7cc384c308 arch: Eliminate the now unused read_code and write_code args. 
Also eliminate the buildReadCode and buildWriteCode methods.

Change-Id: I27b1b87ab51a44b5d7280e29e22f38d97d968a65
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49743
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-12 23:50:52 +00:00
Gabe Black
cfe3ed47a6 arch-x86: Override make(Read|Write) instead of (read|write)_code. 
Change-Id: Iab077f58e19aa6bfeed555caa31a4c8b3d261059
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49741
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
 2022-04-12 23:50:38 +00:00
Matthew Poremba
b64467025d arch-vega: Implement SOP2 S_MUL_HI instructions 
Two new 32-bit signed and unsigned variants of S_MUL were added in
gfx900 which operate similar to S_MUL expect they shift the product by
32 bits after multiplication. Tested with Histogram HIP-Sample and
b+tree in rodinia 3.0 HIP port.

Change-Id: I1bed32b17ccda7aa47f3b59528eb3304912d3610
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58473
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-11 17:06:43 +00:00
Matthew Poremba
e3f65393fd dev-amdgpu,arch-vega: Implement TLB invalidation logic 
Add logic to collect pointers to all GPU TLBs in full system. Implement
the invalid TLBs PM4 packet. The invalidate is done functionally since
there is really no benefit to simulate it with timing and there is no
support in the TLB to do so. This allow application with much larger
data sets which may reuse device memory pages to work in gem5 without
possibly crashing due to a stale translation being leftover in the TLB.

Change-Id: Ia30cce02154d482d8f75b2280409abb8f8375c24
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58470
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-08 17:12:32 +00:00
Chia-You Chen
fb173e4d2c fastmodel: use global option 'num_jobs' instead of hardcoded number 
Change-Id: I2d3f0855c8475cd44b1012fddf6b695621b2347f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58689
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-07 08:09:42 +00:00