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Author SHA1 Message Date
Giacomo Travaglini
78f2f4fd6d dev-arm: generateBasicPioDeviceNode requiring an ArmInterruptPin 
Change-Id: I16ed3b689158defe2a43cccfa053d48dec4a1e41
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31941
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-30 16:06:34 +00:00
Giacomo Travaglini
4a309ae747 dev-arm: Fix DTB autogen for HDLcd 
The HDLcd was wrongly reporting the hardcoded IRQ=63 as the interrupt
number during DTB autogeneration. This is because the DTS is using 63.
However that corresponds to the SPI offset; the gem5 helper is
instead expecting the global IRQ number = 32 + SPI offset

Change-Id: I9e82360843eacb13cef5ddd2e28d2f3ef3147335
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31940
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-30 16:06:34 +00:00
Giacomo Travaglini
4715f6c72c dev-arm: Make the Sp805 use the new ArmInterruptPin::active 
Change-Id: I65b53b33e13345eca93a76e82efac7f8c0b97755
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31939
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-30 16:06:34 +00:00
Giacomo Travaglini
e46aa5c6eb dev-arm: Make Sp804 use the ArmInterruptPin 
Change-Id: I2d71c7e874ba1ec798e2314d7d282cb853b3f360
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31938
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-30 16:06:34 +00:00
Giacomo Travaglini
a1cf1c6c37 dev-arm: Make AmbaInt/DmaDevice use the ArmInterruptPin 
Change-Id: I7318b9186cd81f948211e8a955dab7eea6d2a2f5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31936
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-30 15:44:23 +00:00
Giacomo Travaglini
b722108e0b dev-arm: Make Pl011 UART use the ArmInterruptPin 
Change-Id: I995a424491f087b70b72d2558d96c7a472d4abaa
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31935
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-30 15:44:23 +00:00
Giacomo Travaglini
36d30e1294 dev-arm: Introduce the active boolean for ArmInterruptPin 
The active boolean will specify if the interrupt line is active
or not (high if it is active high or low if it is active low).

This is decoupled from the interrupt being in a pending state
within the GIC, and it can be used by a peripheral to query the
status of its interrupt pin

Change-Id: I18445b891a75767c8a72e9a7044d6d75fdb7e224
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31934
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-30 15:44:23 +00:00
Ian Jiang
78bccaf7a8 sim: Move checkpoint parameters for ptable into seperate section 
In checkpoint output files, the parameters for page table including
size and entries are organized not very clearly. For example:

  [system.cpu.workload]
  ...
  ptable.size=...

  [system.cpu.workload.Entry0]
  vaddr=...
  paddr=...
  flags=...

  [system.cpu.workload.Entry1]
  ...

This commit moves these parameters into a separate section named
'ptable'. For example:

  [system.cpu.workload.ptable]
  size=...

  [system.cpu.workload.ptable.Entry0]
  vaddr=...
  paddr=...
  flags=...

  [system.cpu.workload.ptable.Entry1]
  ...

Change-Id: Iaa4129b3f4f090e8c3651bde90524abba0999c7f
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31874
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-30 07:12:00 +00:00
Gabe Black
a058d66a65 util: Add a "writefile" unit test to the m5 utility. 
Change-Id: Ic0e8d5fbbd5b6d6b57f674cef6460f94206a5872
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27628
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
 2020-07-30 01:01:54 +00:00
Kyle Roarty
42281171ea configs: Change env defaults in apu_se.py for ROCm 
This change simplifies the setup process for running
ROCm-based programs by adding the libraries that are
needed to LD_LIBRARY_PATH by default, using
preexisting environment variables that should be set
on the host.

HOME also gets set, as MIOpen-based programs can fail
without it set.

Change-Id: Ic599674babeaebb52de8a55981d04454cdc96cd8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30275
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
 2020-07-29 18:15:20 +00:00
Chris January
433546a88f fastmodel: Implement GIC DTB auto-generation. 
Implement generateDeviceTree for FastModelGIC so the interrupt
controller is automatically added to the DTB. This is sufficient to
allow a VExpressFastmodel system model to boot Linux without an
explicit DTB.

Change-Id: I69d86fd8bba1b86768c8a118d2de079a56179854
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31078
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-29 08:10:37 +00:00
Chris January
b382bb758f fastmodel: Remove scs_prefix_appli_output binding. 
The scx_prefix_appli_output function is removed in recent Fast Models
releases.

Change-Id: I324b911ec7ed68b7d0c324ac20a9795515e4de57
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31077
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-29 08:10:37 +00:00
Chris January
a29cabb545 fastmodel: Fix hierachical Iris component names. 
Recent releases of Fast Models structure Iris resources in a hierarchy.
Use the parent resource ID if set to construct the hierachical name of
components when constructing the resource map.

Change-Id: Iafafa26d5aff560c3b2e93894f81f770c0e98079
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31076
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-29 08:10:37 +00:00
Chris January
e177e6c372 fastmodel: Add missing dependencies. 
Add -latomic library required by recent Fast Models releases.
Add SystemCExport directory for tlm_has_get_protocol_types.h include.

Change-Id: Ia0c275d55f5077499588228737ed1ff5975cd5db
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31075
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
 2020-07-29 08:10:37 +00:00
Bobby R. Bruce
0f4ecba2a9 base,scons: -wno-deprecated-copy added for hdf5.cc with GCC 
As highlighted by Ciro here:
https://gem5-review.googlesource.com/c/public/gem5/+/31216, and
here: https://gem5.atlassian.net/browse/GEM5-365,  It appears that GCC
versions >= 9 requires `-wno-deprecated-copy` which was removed in
commit: https://gem5-review.googlesource.com/c/public/gem5/+/31216.
`-wno-deprecated-copy` appears to work for all versions of GCC. Clang
does not require `-wno-deprecated-copy` nor `-wno-deprecated` for
sucessfull compilation. Therefore branching has been introduced to the
SConscript to address this and simplify the solution.

Change-Id: I233b32aa945d479dd429bb5591272608ba342d8d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31754
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-29 00:35:00 +00:00
Tony Gutierrez
44807669a0 configs, mem: Support running VIPER with GCN3 
This changeset adds the necessary changes for running
GCN3 ISA with VIPER in apu_se.py.

Changes to the VIPER protocol configs are made to add support
for DMA and scalar caches.

hsaTopology is added to help the pseudo FS create the files
needed by ROCm to understand the device on which the SW is
being run.

Change-Id: I0f47a6a36bb241a26972c0faafafcf332a7d7d1f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30274
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-28 19:01:09 +00:00
Jordi Vaquero
980888eb81 arch-arm: Implement ARM8.1-VHE feature 
This commit implemented the VHE feature in ARMv8. This consist in 3
parts
    1. Register decl/init and register redirection from el1 to el2
        miscregs.cc/hh
        miscregs_types.hh
        isa.cc
        utility.cc/hh
    2. Definition of new EL2&0 translation regime.
        tlb.cc/hh
        table_walker.cc
        pagetable.hh
        tlbi_op.hh
        isa.cc ( for tlb invalidation functions)
    3. Self Debug adaptation for VHE
        self_debug.cc
    4. Effects on AMO/IMO/FMO interruptions
        faults.cc
        interrupts.hh

JIRA: https://gem5.atlassian.net/browse/GEM5-682

Change-Id: I478389322c295b1ec560571071626373a8c2af61
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31177
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-27 17:23:55 +00:00
Kyle Roarty
4b58a1d915 util: Update HIP patch used in gcn Dockerfile 
The new HIP patch includes a change that allows
calls to hipDeviceSynchronize() (and other functions
that call locked_wait()) to run without crashing

Change-Id: Iae6656c19168de696b0f94503e703be67f0baa09
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31794
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-27 16:23:47 +00:00
Gabe Black
cef72adabc util: Standardize console output in the m5 writefile command. 
When the command reports an error, it should then exit(2) and not just
return as if everything worked. When printing the number of bytes
written or the file being opened, it should write this non-error message
to cout, and not cerr.

Also used proper capitalization and punctuation in a couple messages.

Change-Id: I2c0d6592357965ed2eee8f090c8b3d530b354b9f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27627
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-27 08:29:51 +00:00
Gabe Black
deb48638ea util: Add a unit test for the m5 utility's "readfile" command. 
This feeds a fake file to the readfile command which is just a sequence
of incrementing 32 bit values. The incrementing values make sure that
the right region of the input file is being read at the right position,
and the relatively small size means there shouldn't be tons of zeroes
everywhere which can't be distinguished from each other.

Change-Id: I4286b1f92684f127c4885c29192c6c5244a61855
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27608
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
 2020-07-27 08:29:34 +00:00
Gabe Black
135d3e9cf5 util: Add unit tests for most remaining m5 utility commands. 
The only two which still need unit tests are the more complex commands,
readfile and writefile.

Change-Id: Ib9984c71fb4449cbbbd1e2a43f3140975328d31f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27607
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-27 08:29:14 +00:00
Gabe Black
ce90cceb25 util: Add a unit test for the m5 util's "sum" command. 
This change adds the plumbing for and then implements a unit test for
the "sum" command. Despite the fact that this command is very simple,
there are a few things to verify.

1. That args are passed in the right positions.
2. That the number of arguments is checked correctly.
3. That the output to std::cerr is correct.

Change-Id: I71cd473b78fb710cac94df2d70c8d6dc76e5a037
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27566
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-27 08:28:58 +00:00
Gabe Black
8a4fcdee4d util: Make m5 commands return a bool instead of calling usage. 
By delegating actually calling usage() elsewhere, we can remove a dependency
from the commands themselves, and also make testing easier since we won't
exit() every time we call a command with bad arguments.

Change-Id: I6b8e2cb77ce0456b16673f10349362cc53218bba
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27565
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-27 08:28:42 +00:00
Gabe Black
ff82cba034 util: Split up the commands into separate files in the m5 util. 
This way each individual command can have a unit test written for it,
covering how it gathers its arguments and puts them passes them to the
underlying dispatch function.

Change-Id: Ia629c412c8906fc6f5ae02c509ed630755cee45c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27564
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-27 08:28:24 +00:00
Gabe Black
4b1cd4f1a9 util: Add a "command" unit test for the m5 utility. 
This tests the common "command" machinery, but not the individual
commands themselves.

Change-Id: I92769b4cef8210458786e60fd3c01e8e787fb9b2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27563
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
 2020-07-27 08:28:07 +00:00
Gabe Black
692431a89c util: Redistribute command code in the m5 utility. 
This division will make it easier to test both the common command code,
and the individual commands.

Change-Id: Ib7be2b93e40d07e9724443ba26784e45ad9d3b17
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27562
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-27 08:27:41 +00:00
Gabe Black
8096f628fa util: Add a "call_type" unit test to the m5 utility. 
Change-Id: I6ffdf1242a063e776dbb7c18664755773a591b8b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27561
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
 2020-07-27 08:27:21 +00:00
Gabe Black
6a5cf31b04 util: Add an "args" unit test to the m5 utility. 
Change-Id: I7460daaff3301b09e071f2b7e8fb657909805438
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27560
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-27 08:26:41 +00:00
Gabe Black
146dad4f45 util: Make the googletest library available to the m5 utility. 
The library will be available for the abis so that they can test
their unique call mechanisms, and also the main/native environment for
testing shared components.

Build instructions for things that should be built natively, ie unit
tests for common components, should go in the new SConscript.native.

Change-Id: I4a84b2cf2165c92dfb1b6d903b18b45e4cba1352
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27559
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-25 12:01:32 +00:00
Daniel R. Carvalho
1ad015389c mem-ruby: Use lookup function in cache 
There is a function to perform lookups; there is no need to replicate
its code everywhere.

Change-Id: I1290594615d282722cd91071be8ef3c372414e4e
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23946
Reviewed-by: John Alsop <johnathan.alsop@amd.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-25 10:51:06 +00:00
Daniel R. Carvalho
f54af2863c mem-ruby: Cleanup replacement_data usage 
The replacement_data can be assigned as soon as a block is allocated.
With this cleanup the lookup function can be used to avoid code
duplication.

Change-Id: I7561fddaa3ed348866699ecaf1e6aa477ba0bc9a
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23945
Reviewed-by: John Alsop <johnathan.alsop@amd.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-25 10:51:06 +00:00
Matthew Poremba
33f3659825 mem-ruby: Getter/setter for atomic ops in WriteMask 
Adding getter and setter methods for getting and setting the atomic ops
in the WriteMask class. This allows for message types with WriteMasks to
get or set the atomic ops without explicitly modifying the constructor
for the message type. This will beused by the DMASequencer which uses the
SequencerMsg type where the constructor is auto generated via SLICC.

Change-Id: I71787d294c1b89547618e9a13e386b65bb3e1021
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31474
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-24 18:30:08 +00:00
Jordi Vaquero
a5b3a36bf3 arch-arm: Fix Trap to EL1 on register DC CVAU 
Change-Id: I8add9fc8595bb1ac0a7de9778bd4544a01b94ee4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31774
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-24 12:04:12 +00:00
Gabe Black
d4640ffe33 util: Expose the "sum" m5 op in the m5 utility. 
This is just for testing purposes, and can be used to sanity check that
m5 ops work when running a simulation.

Change-Id: I784d033fe4704e60ace5d109beac7bafe1498de6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27558
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-24 04:00:04 +00:00
Gabe Black
cbefc453c4 arch,sim,misc: Add a new m5 op "sum" which just sums its inputs. 
This very simple and mostly useless operation has no side effects, and
can be used to verify that arguments are making it into gem5, being
operated on, and then that a result can be returned into the simulation.

Change-Id: I29bce824078526ff77513c80365f8fad88fef128
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27557
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-24 03:59:49 +00:00
Gabe Black
e3dd8d6114 util: Make the device file name used by map_m5_mem overridable. 
The name this function uses is now exposed as a global variable called
m5_mmap_dev which can be changed at run time.

This would be useful if using a non-standard location for /dev/mem, or
for testing where we might want to use a totally different device.

Change-Id: I5e7ac106c3e4e0555c99af2a7a0aca8171534451
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27556
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-24 03:59:41 +00:00
Gabe Black
cafaccc9d1 util: c++-ify usage printing in the m5 utility. 
Change-Id: Ice8641d490fa9a510a6f1e246530ca5c82ef8170
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27555
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-24 03:59:34 +00:00
Gabe Black
9d222570b8 util: c++-ify the commands in the m5 utility. 
Change-Id: I6755892c42aa418aed64f1aafcdb8c1290b2e8d5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27554
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-24 03:59:18 +00:00
Gabe Black
9f9e725bc6 util: Further consolidate the Args interface in the m5 utility. 
Create static methods to convert any string to an integer or to pack it
into an array of integers. Create non-static methdos named pop() to
pop() the first element and simultaneously convert it. If the conversion
fails, the argument is not popped.

Change-Id: I55d98b3971e7abb7b6206d06ec7fcf046e828d29
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27553
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-24 00:05:00 +00:00
Gabe Black
a216bc70b5 util: Move the m5 utility ABIs into a subdir. 
Change-Id: Ia268fad950c8e7ad9ccfe69af72b57d33f6787b9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27552
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-24 00:04:51 +00:00
Giacomo Travaglini
c23c6ff50a dev-arm: Implement LevelSensitive PPIs in GICv3 
Change-Id: I7f28408eff7d502427c4486518c83506893f4a7a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31516
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-23 16:51:03 +00:00
Giacomo Travaglini
e51f65a440 dev-arm: Implement LevelSensitive SPIs in GICv3 
Change-Id: If918a8aea934f0037818cc64bf458076bfd0251d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31515
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-23 16:51:03 +00:00
Giacomo Travaglini
f441a25204 dev-arm: Gicv3 maintenance interrupt never cleared 
The maintenance interrupt is a level sensitive interrupt though it has
been treated as edge triggered so far.

In order to be level sensitive, it needs to be cleared once the condition
which led to its generation are not valid anymore.

Change-Id: I9af9f4bf27622a7961393b00a145d6c9835d738b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31614
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-23 16:51:03 +00:00
Jordi Vaquero
11e0dccbd5 arch-arm: Add System register trap check for EL1 
This change adds and refactors the register trap checks
for EL1 in the same function, unifying the registry trapping

Change-Id: Ief3e0a9f70cc8cd44c1c8215515f36168927362d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31694
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-23 13:11:13 +00:00
Ciro Santilli
5fe43e8496 cpu: differentiate snoop DPRINTF messages for AtomicSimpleCPU 
Those three snoop messages were the same, which made interpreting logs
harder.

Change-Id: Ibff092932bc6d2ef0c5f15bf5f7ce031d1f1956b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30694
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-23 10:00:40 +00:00
Hoa Nguyen
9058c40908 systemc: Fix systemc array bound error 
Currently, gcc 10.0 does not compile gem5 due to an array bound error
in sc_unsigned and sc_signed constructors.

Previous fix only ignores array-bounds warnings for sc_unsigned.cc and
sc_signed for gcc 10.1 onwards.

This commit turns the ignoring array-bounds warning flag on for all
gcc 10 onwards.

JIRA: https://gem5.atlassian.net/browse/GEM5-677.

Change-Id: Id65b6d52cef527f62917e09231ff79e2237affd8
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31634
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-22 20:10:09 +00:00
Bobby R. Bruce
b99c316840 base,arch: Fixed usage of bitfield::replaceBits 
`bitfield::replaceBits` has two parameters, `first` and `last`, which
relate to the position of the MSB and the LSB of the bits to be replaced
respectively. Therefore `first` >= `last`. In some areas of the
codebase, this assumption has been flipped with `first` <= `last`. This
caused at least one known error, recorded here:
https://gem5.atlassian.net/browse/GEM5-695. These inconsistencies have
therefore been rectified.

A note has been added to the `bitfield::replaceBits` Doxygen to make
the usage of this function clearer.

Change-Id: Ie75856161d9a5684066430ecbdcc52e04e1e77bf
Issue-on: https://gem5.atlassian.net/browse/GEM5-696
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31674
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-22 05:17:33 +00:00
Boris Shingarov
18fff9739c arch-mips: Implement GDB XML target description for MIPS 
Change-Id: Icff3b2c3e60d5989978de854247232afbb3b0dae
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31574
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
 2020-07-21 15:57:00 +00:00
Jordi Vaquero
435d53629f arch-arm: Fix Fault subsystem adding EL2Enable func 
Change-Id: I7a4f0c22ac31fd56a8976ee8a1d9760cf6055d63
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31374
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-21 14:37:54 +00:00
Giacomo Travaglini
e877f715ca dev-arm: Check for security attribute when writing to ICFGR registers 
This is matching the GICD_ICFGR read; a non secure access to a secure
interrupt should be treated as RAZ/WI

Change-Id: I9e92e03c13fe0474ed139b0ed22cebd5847b9109
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31615
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-21 08:55:03 +00:00