derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arch-arm: Fix Trap to EL1 on register DC CVAU

Browse Source 
Change-Id: I8add9fc8595bb1ac0a7de9778bd4544a01b94ee4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31774
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Jordi Vaquero
2020-07-24 10:26:15 +02:00
parent d4640ffe33
commit a5b3a36bf3
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/arch/arm/insts/misc64.cc
View File

@@ -146,7 +146,7 @@ MiscRegOp64::checkEL1Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
break;
case MISCREG_DC_CVAU_Xt:
trap_to_sup = !sctlr.uci && (!hcr.tge || (!scr.ns && !scr.eel2)) &&
el == EL1;
el == EL0;
break;
case MISCREG_CTR_EL0:
trap_to_sup = el == EL0 && !sctlr.uct &&