Commit Graph

13330 Commits

Author SHA1 Message Date
Giacomo Travaglini
776321d2c2 dev-arm: GICD_PIDR2.ArchRev value depends on GIC version
The GIC architecture specification states the GICD_PIDR2.ArchRev
field is set to 3 for GICv3 and to 4 for GICv4. We bind this
value to the gicv4 parameter

Change-Id: I3ba34bc0b4538b4d5170915a4ee042e534f2590f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59391
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2022-05-07 22:40:25 +00:00
Matthew Poremba
54d2438066 dev-amdgpu: Removed hardcoded AQL queue size
The AQL queue size is currently hardcoded to 64kB. For longer running
applications this causes the circular queue to wrap before reaching the
real end of the queue. Add the computation for queue size instead.

Previously longer applications (e.g., bc in pannotia) were hanging
around 4k kernels. With change the application launches 10k+ kernels.

Change-Id: I6c31677c1799a3c9ce28cf4e7e79efcb987e3b7f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59449
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
2022-05-07 03:47:06 +00:00
Giacomo Travaglini
7a9e99400f dev-arm: Gicv3.gicv4 parameter set to False by default
GICv4 features are not currently implemented so it is more natural
to set it to false by default

VExpress_GEM5_V2 platform assumes a GICv4 memory map therefore
sets it to True

Change-Id: Ib4bd17acd56cd029aacf5578ab0259a6ea1bb30c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59390
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2022-05-06 16:29:22 +00:00
Matthew Poremba
c170994676 dev-amdgpu: Fix size issue in interrupt handler
The data allocated for the DMA request used to send an interrupt cookie
was too large. This was causing the memcpy to occasionally seg fault due
to reading past the bounds of the source parameter (the interrupt cookie
struct). Correct the size and add a compile time check to ensure it is
the correct number of bytes expected by the driver.

Change-Id: Ie9757cb52ce8f72354582c36cfd3a7e8a1525484
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58969
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2022-05-05 16:09:49 +00:00
Giacomo Travaglini
7580e8d53d arch-arm: Memoize computeAddrTop in the MMU code
Profiling gem5 has indicated computeAddrTop as one of the main
contributors in AArch64 simulation time

The utility function gets used in the critical path of gem5, which is
the memory translation subsystem. The function is supposed to compute a
rather trivial task: identifying the "real" most significant bit of a
virtual address.

This turns out to be quite expensive. Why?

The main issue is the AArch32/AArch64 check, which uses the ELIs32
helper. This performs a sequential read of several MiscReg
values until it confirms that an EL is indeed using AArch32 (or
AArch64).

This is functionally accurate but it is too expensive for the critical
path of a program.

This patch is addressing the issue by adding a Memoizer object for the
computeAddrTop function to the CachedState data structure, which is
already holding cached system register values for performance reasons.
Whenever we need to invalidate those sys reg values because of a change
in the translation system, we also flush/invalidate the memoizer cache

Change-Id: If42e945c650c293ace304fb4c35e709783bb82d4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59151
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-05-04 14:04:56 +00:00
Bobby R. Bruce
e552295620 stdlib: Allow JSON resources file to be set via env-var
Via the "GEM5_RESOURCE_JSON" environment variable, a user can override
the the default resources.json retrieval location. E.g., a user can have
their own resources.json file and load it instead. This may be a local
file path or a URL.

Code has been changed in downloader.py to allow the loading of
resources.json from either a URL or a local file path. Previously only
URLs were valid.

Change-Id: I022eee58efadc4819069563e9046ce9d84e5cf06
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59069
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-05-03 19:22:57 +00:00
Bobby R. Bruce
d5ebbc1857 stdlib: Update the resources.json URL
It is important this URL remains stable across releases. Pulling
directly from the Google Source git repo is not stable and may change
over time. This patch updates the URL to
https://resources.gem5.org/resources.json. As the gem5.org domain is
under the gem5 project's control, we can ensure this does not change.

Change-Id: I549fabb1525ee1df68cb1641c1bd82ea8bd32262
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59050
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-05-03 19:22:57 +00:00
Hoa Nguyen
46266596ff arch-arm,cpu: Move KVM_CAP_ARM_IRQ_LINE_LAYOUT_2 check to Kvm
This change [1] requires performing KVM_CAP_ARM_IRQ_LINE_LAYOUT_2 check.
However, checkExtension() is only available within the Kvm class and
the KvmVM class.

A new function, Kvm::capIRQLineLayout2(), is added for checking the
status of KVM_CAP_ARM_IRQ_LINE_LAYOUT_2.

This fixes a compilation error on Arm systems.

[1] https://gem5-review.googlesource.com/c/public/gem5/+/55964

Change-Id: Ia190e06ab451e0ff8d1c4833cd23b7de8852c6dd
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59310
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2022-05-03 17:09:05 +00:00
Hoa Nguyen
2938119f97 arch-arm: Fix GenericTimer param name in BaseArmKvmCPU
Per change [1], the new name for `int_virt` is `int_el1_virt`.

[1] https://gem5-review.googlesource.com/c/public/gem5/+/58109

Change-Id: Idde4ac831c7a323b80272642e6a48b1c5e488135
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59309
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2022-05-03 17:09:05 +00:00
Giacomo Travaglini
9c9b3a5e3d arch-arm: Split purifyTaggedAddr in two sub-functions
This patch is splitting the purifyTaggedAddr helper in two
by introducing the maskTaggedAddress utility

* The first part computes the top bit of the address (computeAddrTop)
(This is required as the MSBs of a VA could be used to store
tags like in FEAT_Pauth)

* The second part applies some masking to the supplied
address (maskTaggedAddress) depending on the top bit to
purify the VA from the TAG

The motivation of this split will be clear in the next patch:
we want to memoize the expensive computeAddrTop. Memoizing
purifyTaggedAddr is inefficient as the first argument
is the VA of the memory request so multiple memory requests
will allocate multiple entries in the results cache and
memoization will rarely be used.

We will memoize the VA agnostic computeAddrTop instead

Change-Id: Ib3d8bb521be67a1f21c0891e753396299adf500b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59150
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-05-03 10:40:19 +00:00
Giacomo Travaglini
05cf88e7c2 base: Add generic Memoizer class
This class implements a generic memoization object:

It takes a function as a constructor argument and memoizes
it. Every time the function gets invoked through the Memoizer object
the result gets saved in the internal cache, ready
to be retrieved next time an invokation is made with the same
arguments.

Example usage:

int fibonacci(int n);

Memoizer fibonacci_memo(fibonacci);
fibonacci_memo(5);

There are two ways to discard a memoization

1) Delete the Memoizer object
2) Use the Memoizer::flush method

In some cases there is little or no reason to discard a memoization
(like in the fibonacci example, where fibonacci(k) always returns
the same value for the same input k)
The memoizer could be used in more complex cases, where a change in
the global state affects the output of the function, which
effectively invalidates the cached results.
It is up to the client to understand when memoization is no longer
valid and to flush the result cache as a consequence.

Change-Id: I6cf496b2aef5a66f5375a627165b2cb2e3a1bfc2
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59149
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2022-05-03 10:40:19 +00:00
Giacomo Travaglini
287bea8a4d arch-arm: PAuth inst disassembled with a capitalized first letter
This is not aligned with what we do for other Arm instructions.
This patch removes capitalization of the first letter:

Example

Xpaclri -> xpaclri

Change-Id: I04b3d3b386e34e1dceec940af7c43fc42f538722
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59229
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2022-04-29 09:15:46 +00:00
Yu-hsin Wang
1f713320fe dev: Expose ResetRequestPort constructor
Port::Port is in protected scope. ResetRequestPort should expose the
constructor by itself.

Change-Id: I72ce701fca89379f90e212d7411f481ae1e1977a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59209
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
2022-04-29 02:42:54 +00:00
Kaustav Goswami
fda07590df cpu: nullptr in a DPRINTF statement
This change fixes the crashing of gem5 when `Branch` debug flag
is enabled. A DPRINTF statement had a nullptr. This change
prints `INVALID_TARGET` if the nullptr is encountered.

Signed-off-by: Kaustav Goswami <kggoswami@ucdavis.edu>
Change-Id: I40bd42c07de25a493a3dd1094a2fd8cc0ce0a79b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59109
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2022-04-28 16:57:59 +00:00
Giacomo Travaglini
f8589a4719 sim, arch-riscv: Remove Fault debug flag
There is already a Faults debug flag used by Arm and X86 so
having both Fault and Faults is highly confusing

Change-Id: Id5c17f19b51c6257dfc470d07ba050a9de7a9db3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59152
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-04-28 08:52:49 +00:00
Gabe Black
695c8b7f49 cpu-minor: Use the InvalidRegClass to track invalid RegIds.
Use that instead of the zero register. This avoids two assumptions,
first that there is a zero register in the first place, and second that
the zero register is an integer.

It also avoids referring to the IntRegClass in non-ISA specific code.
It's very likely that all ISAs will have integer registers, but we
should not build in assumptions about what types of registers an ISA has
in general. For instance, not all ISAs have vector predicate registers,
or a scalar floating point register file.

Change-Id: I730fec90f42b90b5be7e1baddf896e18c53e8510
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49711
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2022-04-27 20:27:22 +00:00
Jason Lowe-Power
1e9db5b9cf python: Add error for creating abstact SimObjects
Currently, if you try to instantiate an abstract SimObject the error is
confusing and unhelpful.

"TypeError: _m5.param_<type>.<type>Params: No constructor defined!"

Now, it will instead say "Cannot instantiate an abstract SimObject"
and include the name of the object that causes the error.

Change-Id: Ia8c51e29dccd999ec90dcd39710cc91d9a5fb86f
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59049
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-27 16:56:08 +00:00
Bobby R. Bruce
7f25e7acbf stdlib: Fix race condition in creating of resource dir
Found via a failing weekly test:
https://jenkins.gem5.org/job/weekly/46/

The following exception was thrown:

```
FileExistsError: [Errno 17] File exists: '/nobackup/jenkins/workspace/weekly/tests/gem5/resources'

At:
  /usr/lib/python3.8/os.py(228): makedirs
  build/GCN3_X86/python/gem5/resources/resource.py(156): __init__
  /nobackup/jenkins/workspace/weekly/tests/gem5/configs/x86_boot_exit_run.py(192): <module>
  build/GCN3_X86/python/m5/main.py(440): main
```

It was found that, in cases where the resource directory does not exist,
there is a race condition between gem5 threads to create the directory.
This patch fixes this so threads that lose this race continue normally.

Change-Id: Ie3323c4df0b247e7830c5d3ab93a4d7f9224fe36
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59090
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-26 19:14:34 +00:00
Yu-hsin Wang
9e4c5537a4 fastmodel: Add CortexR52 model reset port
The model reset is an aggregated logic to reset the whole model. The
port helps us to simulate the reboot process.

Change-Id: I15101bfe11dee40b63cc29c2befb610beb3d32aa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58813
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-26 06:31:51 +00:00
Yu-hsin Wang
b4d924fdca fastmodel: Add CortexA76 model reset port
The model reset is an aggregated logic to reset the whole model. The
port helps us to simulate the reboot process.

Change-Id: I9aacc398b299e26e4675f7229db1afc8f6c8a34f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58814
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-26 06:31:51 +00:00
Yu-hsin Wang
8df2ebf43e dev: Add a special reset interface to consolidate reset logic
How to reset a model correctly is very different between models. Take
cpu models for instance, they have different reset pins for different
parts(typically one for each core, one for shared component, one for
debug interface). To make users more easily to reset the model, here we
want to introduce a special reset port. By implementing the port, users
can simply request a whole reset to the model. If users want to do
partial resets, users still can access the raw pins to achieve what they
want.

Change-Id: I746121d16441e021dc3392aeae1a6d9fa33d637a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58810
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-26 06:31:51 +00:00
Samuel Stark
52743eb975 mem-ruby: Support for unaddressed mem requests in the Sequencer
JIRA: https://gem5.atlassian.net/browse/GEM5-1097

Change-Id: I66f7779f447d56e72e1b1f1ca2b84f1b50057542
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57294
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-22 08:55:10 +00:00
Matthew Poremba
8a53add7f8 dev-amdgpu: Fix frame writes for <32-bit writes
In theory a packet between one and eight bytes can be written to frame
buffer memory from the driver. In gem5 pkt->getLE<utin32_t>() will
assert if the packet size is <32-bits. Change to pkt->getUintX(...) to
fix this issue.

Change-Id: If8554013e4ea7bac90985487991d0bf8bdc765ea
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58852
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-21 21:32:53 +00:00
zhongchengyong
29a39d9472 arch-riscv: RISCV call/ret instructions aren't decoded correctly
This change adds IsReturn and IsCall flag for RISC-V jump instructions
by define new "JumpConstructor" in standard.isa, and fixes target
overwriting in buildRetPC.

See RAS presentation in spec:
Section 2.5 Page 22 of https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf
Or:
https://github.com/riscv/riscv-isa-manual/blob/master/src/rv32.tex#:~:text=Return%2Daddress%20prediction,%5Cend%7Btable%7D

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1139

Change-Id: I9728757c9f3f81bd498a0ba04664a003dbded3bf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58209
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-21 06:34:40 +00:00
Sungkeun Kim
af534729c4 mem-garnet: Packet Tracing of garnet network
This is a patch to keep track of
a single packet in the garnet network.
This patch would help for finding a deadlock issue
during the extending the garnet network.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1181

Change-Id: I1138484807ef127a3240b46154e29ae77678f1e9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58857
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Maintainer: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-21 01:23:24 +00:00
Bobby R. Bruce
74f3f190fb stdlib: Add tar unpacking to downloader
With this commit gem5-resources can exist as tarballs to be unpacked
after download. This requires the field "is_tar_archive : true" to be
present in the resource description in resources.json.

Change-Id: Ia835c1777425a5aafe8ba7ee9c725edf6d45f68c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58851
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-19 22:01:00 +00:00
Bobby R. Bruce
e33f9b830b stdlib: Update the stdlib resource's md5 utils
The commit does the following:

- Moves the md5 functions to their own Python module (this will allow us
to use this elsewhere).
- Add functionality to enable md5 values for directories.
- Adds Pyunit tests for the md5 functionality.

Change-Id: I224d4584ed6c35fac3a75e221b3cb48d863ffa6f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58849
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
2022-04-19 22:01:00 +00:00
Gabe Black
6d8a5ad2ad stdlib: Add missing ()s in get_supported_isas.
A function was used directly instead of being called when interating
through ISA names.

Change-Id: I9dc53259a766a68070e0b79bb55f721a93fcdeed
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58929
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-17 01:07:55 +00:00
Jerin Joy
70fd98e807 arch-riscv: Added the Zbs bitmanip instructions
Added the bclr, bclri, bext, bexti, binv, binvi, bset, bseti
instructions.

Changes based on spec:
https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0.pdf

Change-Id: I126d659d973b250b642bd56b3b149f0ee6a3323e
Signed-off-by: Jerin Joy <joy@rivosinc.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58632
Reviewed-by: Luming Wang <wlm199558@126.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2022-04-13 20:09:59 +00:00
Jerin Joy
df886bc8c1 arch-riscv: Added the Zbc bitmanip instructions
Added clmul, clmulh, clmulr instructions.

Changes based on spec:
https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0.pdf

Change-Id: I98dc76ddde052f56e32eabed12af87039def665b
Signed-off-by: Jerin Joy <joy@rivosinc.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58631
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Luming Wang <wlm199558@126.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-13 20:09:59 +00:00
Jerin Joy
aee1622a6c arch-riscv: Added the Zba and Zbb bitmanip instructions
Zba instructions added:
add.uw, sh1add, sh1add.uw, sh2add, sh2add.uw, sh3add, sh3add.uw, slli.uw

Zbb instructions added:
andn, orn, xnor, clz, clzw, ctz, ctzw, cpop, cpopw, max, maxu, min,
minu, sext.b, sext.h, zext.h, rol, rolw, ror, rori, roriw, rorw, orc.b, rev8

Changes based on spec:
https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0.pdf

Change-Id: I056719f62eee89e0f085d1bf1fa182f9dfe614d8
Signed-off-by: Jerin Joy <joy@rivosinc.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58630
Reviewed-by: Luming Wang <wlm199558@126.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-13 20:09:59 +00:00
Yu-hsin Wang
72255064d6 fastmodel: Export more CortexR52 reset pin
Change-Id: I20f34ae2061e886b35fe9439dbb8e25ce3571e4f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58811
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-13 08:44:03 +00:00
Yu-hsin Wang
9dce95844a fastmodel: Export more CortexA76 reset pin
Change-Id: I386cf659fa77b2005f808fde51ef772ac0a57735
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58812
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-13 08:44:03 +00:00
Gabe Black
7392cd470e scons: Ensure the fast model license count is always at least 1.
Even though the default value for the license count is 1, it seems that
if fast model is disabled, kconfig will set it to 0. When creating a
cycle using itertools over a list with zero elements, it will raise a
StopIteration.

Even though we don't actually try to build any fast model components
in that case, we do still set them up with a license slot. If the
cycle iterator is essentially broken, that will prevent that from
working and break the build.

This change forces the license count to be at least 1, even if fast
model is disabled and the license count may be set to 0 in the config.

Change-Id: Ia8df256a8f292deb6fb6fa3c5f9a7d58c2b7f782
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58490
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-13 02:16:13 +00:00
Gabe Black
7cc384c308 arch: Eliminate the now unused read_code and write_code args.
Also eliminate the buildReadCode and buildWriteCode methods.

Change-Id: I27b1b87ab51a44b5d7280e29e22f38d97d968a65
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49743
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-12 23:50:52 +00:00
Gabe Black
cfe3ed47a6 arch-x86: Override make(Read|Write) instead of (read|write)_code.
Change-Id: Iab077f58e19aa6bfeed555caa31a4c8b3d261059
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49741
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2022-04-12 23:50:38 +00:00
Tiago Mück
eb0b4ba657 mem-ruby: CHI fix for WUs on local+upstream line
Fix for WriteUnique operations on cache lines that are both local and
upstream

JIRA: https://gem5.atlassian.net/browse/GEM5-1097

Change-Id: I99def32948d3f0ced9cfc7f7712a0f4ae9aab0cd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57299
Reviewed-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-12 10:21:57 +00:00
Matthew Poremba
b64467025d arch-vega: Implement SOP2 S_MUL_HI instructions
Two new 32-bit signed and unsigned variants of S_MUL were added in
gfx900 which operate similar to S_MUL expect they shift the product by
32 bits after multiplication. Tested with Histogram HIP-Sample and
b+tree in rodinia 3.0 HIP port.

Change-Id: I1bed32b17ccda7aa47f3b59528eb3304912d3610
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58473
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-11 17:06:43 +00:00
Samuel Stark
7e84a14a26 mem-ruby: AbstractController unaddressed profiling
Adds support for profiling "unaddressed" transactions,
which are associated with a unique ID rather than a memory address,
to AbstractController.

JIRA: https://gem5.atlassian.net/browse/GEM5-1097

Change-Id: Ib75f3f38dc4910acc2ad4f1c7bf88c9193568203
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57297
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-11 09:57:43 +00:00
Samuel Stark
920859e191 mem-ruby: Added upstream_nodes to AbstractController
Added support for an upstream_nodes NetAddr list in AbstractController,
which will be used in future CHI work.

JIRA: https://gem5.atlassian.net/browse/GEM5-1097

Change-Id: I30a6d621d7f201d89f0b13dab8ed4dd1f1f6caa3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57296
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-11 09:57:43 +00:00
Samuel Stark
65f8bf4460 mem-ruby: Support for unaddressed mem requests in the RubyRequest
JIRA: https://gem5.atlassian.net/browse/GEM5-1097

Change-Id: I5aa44186888b95f81bec524ff57e8dbf4c9166f8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57293
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-11 07:31:34 +00:00
Samuel Stark
32ed7794d8 mem-ruby: Add TLBI callbacks to the RubyPort
JIRA: https://gem5.atlassian.net/browse/GEM5-1097

Change-Id: I984fd497b7209772106150abb853c91c3d818dfd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57295
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-11 07:31:34 +00:00
Samuel Stark
6dac25a7f4 cpu: Handle external TLBI Sync requests in O3CPU
JIRA: https://gem5.atlassian.net/browse/GEM5-1097

Change-Id: I02e55a42e0f717211b481e65d59900fc3d05f061
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57292
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-11 07:31:34 +00:00
Matthew Poremba
8fe975e57e gpu-compute: Fatal on dynamic scratch allocation in GPUFS
This is known not working in GPUFS. As a result, the simulation will
never end. Rather than simulate forever, add a fatal for now to exit
simulation until support for this functionality is added.

Change-Id: I8e45996a7eb781575e8643baea05daf87bc5f1c3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58472
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-08 17:12:32 +00:00
Matthew Poremba
1562251243 dev-amdgpu: Update comments pointing to ROCK repo
It seems the tag name was changed which broke a few links in some
comments pointing to where definitions and struct come from. Update the
URLs and also use consistent version.

Change-Id: I7d6393f1f08d592989999a8a6f9c5bbdf1a9c992
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58471
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-08 17:12:32 +00:00
Matthew Poremba
e3f65393fd dev-amdgpu,arch-vega: Implement TLB invalidation logic
Add logic to collect pointers to all GPU TLBs in full system. Implement
the invalid TLBs PM4 packet. The invalidate is done functionally since
there is really no benefit to simulate it with timing and there is no
support in the TLB to do so. This allow application with much larger
data sets which may reuse device memory pages to work in gem5 without
possibly crashing due to a stale translation being leftover in the TLB.

Change-Id: Ia30cce02154d482d8f75b2280409abb8f8375c24
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58470
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-08 17:12:32 +00:00
Cui Jin
19bf5c4f33 cpu-o3: Resolve circular buffer issue for LSQ
--since int is only 4 bytes, while ssize_t is 8 bytes in 64bit
  system. so 0x80000000 is regarded as negative value.

Jira Issue:: https://gem5.atlassian.net/browse/GEM5-1203

Change-Id: I74b3785b29751f777f5e154692fa60bf62b37b9f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58649
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-08 15:40:30 +00:00
Bobby R. Bruce
c296940103 stdlib: Fixing resources.json caching for multi-user envs
The downloader briefly caches the resources.json file in "/tmp". This
works fine if the system only has one user, but in a system supporting
many users, where "/tmp" is shared, there were permission issues when a
user tried to access a resources.json cache from another user. To
resolve this the uid of the user is appended to the filename.

Change-Id: Iba8ab12cd7054c2f5636e444ac0f1f8f73fedc89
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58489
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-08 04:05:23 +00:00
Gabe Black
8a91e933e8 scons: Use the 'png' tag for the PNG library.
Use that instead of checking HAVE_PNG manually.

Change-Id: I70876982c2506bee1173341fa100f5fae2ae4302
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58709
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-07 20:47:23 +00:00
Matthew Poremba
e36a8dbd8a gpu-compute: Handle GPUFS system store responses
Requests in GPUFS which go to system memory will not generate the
WriteCompleteResp packets that the VIPER protocol would normally created
for device requests which go through the caches. Therefore, we need to
callback the GM pipe handleResponse to complete the access and make
forward progress.

Change-Id: Ic00c430ce420a591fe5743f758b780d93afd2a38
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57989
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-07 20:11:01 +00:00