Commit Graph

10 Commits

Author SHA1 Message Date
Hoa Nguyen
4c42811ff3 mem-ruby: Move CacheMemory stats used in SLICC to a Stats group
This change moves some stats that are used in SLICC to a
separate Stats::Group.

In order to use stats in SLICC, new functions are added in
CacheMemory:
        - profileDemandHit()
        - profileDemandMiss()

The functions increase the corresponding stat by 1.

Change-Id: I52b6fefdf6579a49f626f2fca400641f90800017
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37815
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Tiago Mück <tiago.muck@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-12-22 09:52:36 +00:00
Timothy Hayes
0a8a787de3 mem-ruby: HTM mem implementation
This patch augments the MESI_Three_Level Ruby protocol with hardware
transactional memory support.

The HTM implementation relies on buffering of speculative memory updates.
The core notifies the L0 cache controller that a new transaction has
started and the controller in turn places itself in transactional state
(htmTransactionalState := true).

When operating in transactional state, the usual MESI protocol changes
slightly. Lines loaded or stored are marked as part of a transaction's
read and write set respectively. If there is an invalidation request to
cache line in the read/write set, the transaction is marked as failed.
Similarly, if there is a read request by another core to a speculatively
written cache line, i.e. in the write set, the transaction is marked as
failed. If failed, all subsequent loads and stores from the core are
made benign, i.e. made into NOPS at the cache controller, and responses
are marked to indicate that the transactional state has failed. When the
core receives these marked responses, it generates a HtmFailureFault
with the reason for the transaction failure. Servicing this fault does
two things--

(a) Restores the architectural checkpoint
(b) Sends an HTM abort signal to the cache controller

The restoration includes all registers in the checkpoint as well as the
program counter of the instruction before the transaction started.

The abort signal is sent to the L0 cache controller and resets the
failed transactional state. It resets the transactional read and write
sets and invalidates any speculatively written cache lines.  It also
exits the transactional state so that the MESI protocol operates as
usual.

Alternatively, if the instructions within a transaction complete without
triggering a HtmFailureFault, the transaction can be committed. The core
is responsible for notifying the cache controller that the transaction
is complete and the cache controller makes all speculative writes
visible to the rest of the system and exits the transactional state.

Notifting the cache controller is done through HtmCmd Requests which are
a subtype of Load Requests.

KUDOS:
The code is based on a previous pull request by Pradip Vallathol who
developed HTM and TSX support in Gem5 as part of his master’s thesis:

http://reviews.gem5.org/r/2308/index.html

JIRA: https://gem5.atlassian.net/browse/GEM5-587

Change-Id: Icc328df93363486e923b8bd54f4d77741d8f5650
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30319
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-09-08 09:13:30 +00:00
Timothy Hayes
203efba46a mem-ruby: MESI_Three_level prefetcher support
Add support for the Ruby stride prefetcher to MESI_Three_Level.

Change-Id: Id68935e2a7d3ccd0e22a59f43a15f167410632a2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27715
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-02 06:50:44 +00:00
Timothy Hayes
af1f3b35b0 mem-ruby: fix MESI_Three_Level erroneous transition
The MESI_Three_Level protocol includes a transition in its L1
definition to invalidate an SM state but this transition does
not notify the L0 cache. The unintended side effect of this
allows stale values to be read by the L0 cache. This can cause
incorrect behaviour when executing LL/SC based mutexes. This
patch ensures that all invalidates to SM states are exposed to
the L0 cache.

Change-Id: I7fefabdaa8027fdfa4c9c362abd7e467493196aa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28047
Reviewed-by: John Alsop <johnathan.alsop@amd.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-02 02:37:50 +00:00
Timothy Hayes
2c8b7bfe52 mem-ruby: MESI_Three_Level discriminate L0 invalidation reason
The L0 cache can now know whether a line is being invalidated
due to this cache/core's own requirements, e.g. a load from the core
causing a line eviction, or due to another cache/core's requirements,
e.g. a remote cache requesting a present line in exclusive state.

Change-Id: If57bfb92b6c8f575ca47d984606be7c859dcff9a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24259
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2020-03-20 13:25:11 +00:00
Timothy Hayes
a3d348cca7 mem-ruby: MESI_Three_Level fix L1 MRU absence
The L1 cache is updating the MRU tag after acessing a cache line.
This patch updates MRU for cases when the L0 cache loads/stores
a line from/to the L1 cache.

Change-Id: I1f0ccef26b3c7614dc865a38c39145840dabfd01
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24258
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2020-03-20 13:25:11 +00:00
Timothy Hayes
8430889fa7 mem-ruby: MESI_Three_Level fix L1 in_port ranks
The L1 cache contains three in_port networks with ranks 0-2-3.
This is a benign typo, however, this patch corrects the ranks to
0-1-2 for clarity.

Change-Id: Id9bb63dae310af0f962345a114b0ccb8bddcf696
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24257
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2020-03-20 13:25:11 +00:00
Timothy Hayes
9f9606fb63 mem-ruby: MESI_Three_level HTML reference generation fix
The SLICC HTML generator does not work without the 'desc' property of
the STATES and EVENTS found in the protocol state machine source files.
This adds the 'desc' property in MESI_Three_Level to declarations where
it was missing and cleans up the text of some existing ones.

Issue-on: https://gem5.atlassian.net/browse/GEM5-357

Change-Id: I2d0f8e11889554063fed798e724217963d4a74de
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24256
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-03-20 09:39:43 +00:00
Jing Qu
aff2cad4be mem-ruby: prevent cacheProbe being called multiple times
The cacheProbe() function will return the victim entry, and it gets
called for multiple times in trigger function in a single miss. This
will cause a problem when we try to add a new replacement policy to
the Ruby system. Certain policy, like RRIP, will modify the block
information every time the getVictim() function gets called. To
prevent future problems, we need to store the victim entry, so that
we only call it once in one miss.

Change-Id: Ic5ca05f789d9bbfb963b8e993ef707020f243702
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21099
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-25 18:47:54 +00:00
Gabe Black
c08351f4d3 mem: Move ruby protocols into a directory called ruby_protocol.
Now that the gem5 protocols are split out, it would be nice to put them
in their own protocol directory. It's also confusing to have files
called *_protocol which are not in the protocol directory.

Change-Id: I7475ee111630050a2421816dfd290921baab9f71
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20230
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-23 21:13:07 +00:00