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mem-ruby: MESI_Three_Level fix L1 MRU absence

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The L1 cache is updating the MRU tag after acessing a cache line.
This patch updates MRU for cases when the L0 cache loads/stores
a line from/to the L1 cache.

Change-Id: I1f0ccef26b3c7614dc865a38c39145840dabfd01
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24258
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Timothy Hayes
2019-10-18 16:53:59 +01:00
committed by Giacomo Travaglini
parent 8430889fa7
commit a3d348cca7
1 changed files with 4 additions and 0 deletions
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4
src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
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@@ -617,6 +617,8 @@ machine(MachineType:L1Cache, "MESI Directory L1 Cache CMP")
out_msg.DataBlk := cache_entry.DataBlk;
out_msg.MessageSize := MessageSizeType:Response_Data;
}
cache.setMRU(address);
}
action(hh_xdata_to_l0, "\h", desc="If not prefetch, notify sequencer that store completed.") {
@@ -633,6 +635,8 @@ machine(MachineType:L1Cache, "MESI Directory L1 Cache CMP")
//cache_entry.Dirty := true;
}
cache.setMRU(address);
}
action(h_stale_data_to_l0, "hs", desc="If not prefetch, send data to the L0 cache.") {