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11521 Commits

Author SHA1 Message Date
Tiago Mück
2d13fa1f73 mem-ruby: removes data ptr from RubyRequest 
It's redundant since we keep the PacketPtr.

Change-Id: I421ffe8a25ad6a96454d84c0726715fd87a451e6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41113
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-02-16 17:55:32 +00:00
Matthew Poremba
391322ff9b cpu,configs: Add DMA thread to Ruby GPU tester 
Add a DMA thread tester to the Ruby GPU tester to test the DMA state
machine in the protocol. Currently creates a dummy DMA device to pass
through Ruby.py and scans for the DMA sequencers due to opaqueness of
Ruby.py.

DMA atomics not yet supported as there is no protocol that implements
atomic transitions in the DMA state machine file.

Example run command:
build/GCN3_X86/gem5.opt configs/example/ruby_gpu_random_test.py \
    --test-length=1000

Change-Id: I63d83e00fd0dcbb1e34c6704d1c2d49ed4e77722
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39936
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-02-16 16:48:57 +00:00
Matthew Poremba
2b0ab1f48e cpu: Rename GpuThread in gpu_ruby_test tester 
The GpuThread class will be used as an abstract class for any thread
type (CPU, GPU, DMA) therefore changing to a more appropriate name.

Change-Id: If241edb53ea405c95b0315c609176c6470b29931
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39935
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-02-16 16:48:57 +00:00
Matthew Poremba
bd02699932 mem-ruby: Make DMASequencer aware of Atomics 
Add handling for issuing atomic packet types, setting the WriteMask and
AtomicOpFunctor in makeRequest. Add an atomicCallback to handle atomic
packet type responses.

Change-Id: I9775fc110bb99a1740089746f0d1b3deb124b9f5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33716
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-02-16 16:48:57 +00:00
Giacomo Travaglini
890364122d python: Sort py sources in alphabetical order 
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: Id61b47389fdd72573c0a450eb86f802d05667e93
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41313
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-02-16 10:33:18 +00:00
Giacomo Travaglini
c495339344 dev-arm: Fix PL111 address range 
The device was using an incorrect range size (0xFFFF) instead of
0x10000

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I57ddfdb171351b606c63fcc90bcf0126c9ae76da
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41293
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2021-02-16 10:33:04 +00:00
Gabe Black
d37a0dab73 arch: Get rid of global maximums for numbers of source/dest/misc regs. 
Change-Id: I6881572daedf0f0e9ff6aee4f174671d02ef743d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38389
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
 2021-02-15 19:21:21 +00:00
Giacomo Travaglini
928d29d1a7 dev-arm: Fix GICv3 address range 
Distributor and Redistributor sizes should be 64KiB and 128KiB (gicv4)

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I7f9696c5911840d88f4db10379f8cd62fa06a718
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41294
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-02-15 13:53:30 +00:00
Daniel R. Carvalho
5a47a830d3 base: Add enum to_number tests 
Add a test to convert a string containing a number into enums.

One of the tests has been disabled to highlight an error-prone
situation where a number that is not a valid enum manages to
be converted to an enum.

Change-Id: I7967c62feea335f3ffda40d8bf0334c20b53ee6c
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41334
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
 2021-02-15 03:05:29 +00:00
Gabe Black
e16301f96b arch-x86: Use popCount from bitfields.hh. 
Use popCount from bitfields.hh rather than call __builtin_popcountl
directly. That will ensure the instruction works whether or not that
builtin is available.

Change-Id: I947b35bb832b768936b489a58ee324adb8a90b5e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41354
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-02-13 08:46:05 +00:00
Gabe Black
13cda5a734 arch: Stop including unnecessary FP headers. 
Nothing is used from them. They're probably there as copy/paste from
other ISAs, or old code that's been replaced. This also gets rid of some
 #if guarded includes which is a nice cleanup.

Change-Id: Icd84300fb7531ec203ce4acbdae1d311e56cc873
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41353
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-02-13 08:45:56 +00:00
Tiago Mück
9c4809b9ab mem-ruby: intToTick helper 
Change-Id: I76635228223e9a83eef94a25d166d091315a5e96
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41156
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-02-12 20:31:38 +00:00
Tiago Mück
fc3832dfaa mem-ruby: add wakeup_port statement 
While the wakeUpBuffers/wakeUpAllBuffers check all message buffers,
wakeup_port wakes up only the messages stalled on the specified port
and address. Usage is the same as the stall_and_wait statement, e.g.:

wakeup_port(reqInPort, addr);

Change-Id: I57dc77d574c0016ca55786ce16a73061a1d37f2e
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41155
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-02-12 20:31:38 +00:00
Tiago Mück
d789b75a98 mem-ruby: add andMask to WriteMask 
Change-Id: Ieeb68b405a68226077a2ffee231408f554e758a5
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41154
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-02-11 22:16:29 +00:00
Tiago Mück
8839beb492 python: more readable Ruby dot topology 
Controllers may have the same name under different parents, thus
the controller full path is used as label. To avoid long and redundant
labels, common prefixes and suffixes are removed from the path.

Change-Id: Id793b59a4c38f3425ae5348138ae1d74c823edd7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41093
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-02-11 22:13:38 +00:00
Kyle Roarty
dd270656f0 arch-gcn3: Fix sign extension for branches with multiplied offset 
Certain branch instructions specify that the result of (simm16 * 4)
gets sign-extended before being added to the PC.

Previously, that result was being sign extended as if it was still a
16-bit number. This patch fixes that by having the result be sign
extended as an 18-bit number.

Change-Id: Id4d430f8daa71ca7910b570e7e39790626f1decf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41053
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-02-11 20:08:25 +00:00
Tiago Mück
1861bc39ea mem-ruby: fix Sequencer latency reporting 
Most protocols won't set initialRequestTime, forwardRequestTime, and
firstResponseTime, thus leading to calculated latency being always 0.

Change-Id: Id2c73314a964bf6efb262d40b3df515373023b84
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41114
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-02-11 17:12:22 +00:00
Tiago Mück
c1cb1f2f93 mem-ruby: fix functional reads in abstract ctrl 
When calling functionalMemoryRead we need to check the mem req. queue
first as it may have write data not yet forwarded to the memory port.

Change-Id: Id37aa0837a3462d92ae9ac3b45ca756b2c4f7d97
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41153
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-02-11 17:11:33 +00:00
Tiago Mück
0183c58492 mem-ruby: fixes for masked writes 
This adds DataBlock::setData(PacketPtr) to update the block with
packet data. The method uses the packet's writeData to copy the
correct bytes if the request is a masked write.

Change-Id: I9e5f70fed29edcf55fef94a4b145aa838dc60eac
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41134
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-02-11 17:05:01 +00:00
Tiago Mück
dde0e3f0df mem-ruby: warns on masked functional writes 
It's not expected to issue masked functional writes or to receive
functional writes to an address with a pending masked write.

Change-Id: Ibc8ba5f642ff72f897e3a50011c0da6d3000b741
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41133
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-02-11 17:05:01 +00:00
Giacomo Travaglini
be08e29991 arch-arm: Fix CPTR_EL2 writes 
* If E2H==1, CPTR_EL2.ZEN bits are not RES0.
* If E2H==1, CPTR_EL2.FPEN bits are not RES0.

Change-Id: Ic82b266975d89056d7c2f55464bd8a0c18a43e03
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39702
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-02-11 09:45:10 +00:00
Hoa Nguyen
0bc0c0b9eb mem: Initialize pendingWrites stat of NVMStats 
The initialization for this stat was mistakenly removed here
https://gem5-review.googlesource.com/c/public/gem5/+/39276

Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: I27b6ddf6d6b925c9787acb07552a8d5acb081c22
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41073
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-02-10 21:56:20 +00:00
Daniel R. Carvalho
205fe472ad base: Fix copyright of base/stats/SConscript 
The original copyright was accidentally removed by
e59557af50.

Change-Id: Ib3b7a34ea889fbd9a6f2a8e21a6bb24432939da9
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40755
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-02-10 14:18:58 +00:00
Gabe Black
51ca61dbf6 scons: Remove partial linking. 
This feature didn't actually provide any benefit in the end, and
increased build directory size and scons complexity.

Change-Id: Ia5aa16a8dd008599645076cea8131799f6086e0f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40795
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-02-10 11:34:19 +00:00
Gabe Black
ca3670fbd1 cpu: Delete the empty, default off "nocpu". 
This very nearly empty CPU directory does nothing except define a CPU at
the scons level which is off by default. It seems safe to delete it.

Change-Id: I5bd3a52062bbc67fb1ee7d350519cd85a3f8fdb8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40871
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
 2021-02-10 11:33:46 +00:00
Giacomo Travaglini
e2b0cecef9 dev-arm: Add VRAM to VExpress_GEM5_Base 
Change-Id: Ibd3ae59730c6d00a6bd8b129f973b79a565f66e4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40973
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-02-10 09:08:52 +00:00
Hoa Nguyen
0367539e9f cpu: Remove units from stats description 
A recent change https://gem5-review.googlesource.com/c/public/gem5/+/40622
allows units to be shown in stats dump; the units in stats
descriptions are nolonger necessary. This change removes units
from stats descriptions. However, for units that are multiples
of a supported unit (e.g. MegaBytes), the units

Change-Id: Ib63ea44e757f755f761b20b40e045bc37c90baff
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40735
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
 2021-02-10 09:03:09 +00:00
Hoa Nguyen
26d2731e5f arch-riscv: Fixed the style of stats variable names in TlbStats 
The variable names should be of camel case style.

Change-Id: I397c9f165a53ecc120ec57f7214c90a65e12407e
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40695
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
 2021-02-10 09:03:09 +00:00
Hoa Nguyen
42e0247507 dev,dev-arm: Remove units from stats description 
A recent change https://gem5-review.googlesource.com/c/public/gem5/+/40622
allows units to be shown in stats dump; the units in stats
descriptions are nolonger necessary. This change removes units
from stats descriptions. However, for units that are multiples
of a supported unit (e.g. MegaBytes), the units in the descriptions
are kept until unit prefixes are supported.

Change-Id: I199afbf29fee13b08eeb323c4cb56c8a974dbe94
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40675
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
 2021-02-10 09:03:09 +00:00
Hoa Nguyen
5aaa392f2e mem: Remove units from stats description 
The change https://gem5-review.googlesource.com/c/public/gem5/+/40622
allows units to be shown in stats dump, the units in stats
descriptions are nolonger necessary. This change removes units
from stats descriptions. However, for units that are multiples
of a supported unit (e.g. MegaBytes), the units in the descriptions
are kept until unit prefixes are supported.

Change-Id: I4d87139290a8458e87da776e4328edbd6c224546
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40655
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
 2021-02-10 09:03:09 +00:00
Hoa Nguyen
67f5f1c3e3 base-stats: Print Units in Stats dump 
Change-Id: I8fba4f19805c3149175ff730d014383dcaa1bf81
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40622
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-02-10 09:03:09 +00:00
Hoa Nguyen
489e72d509 mem: Change warmupCycle stat to warmupTick 
Change-Id: I96399dc5c062479049e7bf0de91d9f4f97903c43
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40575
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
 2021-02-10 09:03:09 +00:00
Hoa Nguyen
65bbd5fa2a cpu: Add Units to cpu stats 
Change-Id: I387b2e9f6ecf62757242056f732bd443c457ebea
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39095
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
 2021-02-10 09:03:09 +00:00
Hoa Nguyen
c5c0dd9a24 learning-gem5: Add units to stats 
Change-Id: Iaff6c19b0b87250d15f5afb0763680fafe782d52
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39417
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
 2021-02-10 09:03:09 +00:00
Hoa Nguyen
9625e90b8e arch-arm,arch-riscv,arch-x86: Add units to stats 
Change-Id: I6bf506c223207306d71511491e024546b209030f
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39416
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
 2021-02-10 09:03:09 +00:00
Hoa Nguyen
4ab768c54e dev,dev-arm: Add units to stats in /src/dev 
Change-Id: I9d2449ef173f2f467717a9d233aef8d9a2f43f26
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39415
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
 2021-02-10 09:03:09 +00:00
Hoa Nguyen
eade85fa50 sim: Add units to src/sim 
Change-Id: I5fa147aa1319d62be1790bbd74fd097ac566f808
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39296
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
 2021-02-10 09:03:09 +00:00
Hoa Nguyen
c720e26c85 mem: Add Units to mem stats 
Add units to mem stats except mem-ruby stats

Change-Id: Iab214b5d08eb1accc2b35af0c3aed7d30df5b5f3
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39276
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-02-10 09:03:09 +00:00
Hoa Nguyen
1f1decd765 cpu,mem: Converting stats to supported units 
There are several stats having unit being a multiple of supported
units. This change makes the following conversions:
  * MiB/s -> bytes/s
  * percentage -> ratio

Change-Id: I9832796e87698daa7f87f91fa39ce40bbf92e737
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41013
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
 2021-02-10 09:03:09 +00:00
Hoa Nguyen
14732c4f97 mem: Fix/Improve stats in src/mem 
* Improved/Fixed the stat description of several stats.
* Fixed the value assigned to `warmupCycle` stat of cache tags,
it was set to curTick().
* Use ADD_STAT in CacheCmdStats.

Change-Id: Iabff7d42318fcc73df79ee7f3c5430f4c45555e5
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39975
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-02-10 09:03:09 +00:00
Hoa Nguyen
e331aa9718 base-stats: Add Units to Stats 
This commit adds an option to add SI and its derived units to stats.

Units are now the third parameter of every Stat class constructor.

The following are convenient macros that could be used to add units
to stats,
   * UNIT_CYCLE: represents clock cycles.
   * UNIT_TICK: represents the count of gem5's Tick.
   * UNIT_SECOND: represents the base unit of time defined by SI.
   * UNIT_BIT: represents the number of computer bits.
   * UNIT_BYTE: represents 8 bits.
   * UNIT_VOLT: a SI derived unit measuring potential difference.
   * UNIT_JOULE: represents joule, a unit of energy, as defined by SI.
   * UNIT_WATT: represents 1 watt, where 1 watt = 1 joule / second.
   * UNIT_CELSIUS: represents 1 Celsius degree as defined by SI.
   * UNIT_RATE(T1, T2): represents the unit of a quantity of T1 divided
                        by a quantity of T2.
   * UNIT_RATIO: represents the unit of a quantity of unit T divided by
                 a quantity of unit T.
   * UNIT_UNSPECIFIED: the unit of the stat is unspecified. This type of
                       unit is mainly for backward compatibility. Newly
                       introduced stats should have the units specified.

This commit also alters the behavior of the ADD_STAT macro.
Specifically, ADD_STAT syntax is unchanged, but the unit of the stat
is hardcoded to be UNIT_UNSPECIFIED.

JIRA link: https://gem5.atlassian.net/browse/GEM5-849

This change is an effort towards supporting new stats schema:
https://github.com/gem5/stats-schema

Change-Id: I791704a6c4d9e06332797dbfc5eb611cb43f4710
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38855
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
 2021-02-10 09:03:09 +00:00
Gabe Black
134c37ca3e cpu: Track misc regs in vectors in the O3 CPU instruction class. 
Most instructions won't actually write to misc regs, so the overhead
should be quite small, particularlly compared to the other overheads in
the O3.

Change-Id: I840d6002cc8151f91611cfcbe2bfa52acc284c0f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38388
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
 2021-02-10 06:25:12 +00:00
Gabe Black
776822d147 cpu: Track flat register indices in the Minor CPU with a vector. 
That avoids having to know the maximum number of dest registers there
can be in any instruction, and will likely not affect the performance of
the Minor CPU overall.

Change-Id: I4e49695ba06365d52eb4ce128d5cbb30db665bd7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38387
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
 2021-02-10 06:25:06 +00:00
Gabe Black
08aa5351c0 cpu: Factor MaxInst(SrcDest)Regs out of the trace CPU. 
Manage register and ROB dependencies using lists instead of arrays to
better support random removals, and avoid having to know the global
maximum number of registers in an instruction.

Change-Id: Ie9f30c61bac52ad31745a1011f62c95622908d2f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38386
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-02-10 06:07:09 +00:00
David Schall
f7e0115882 base: Add XOR and modulo operator to ChannelAddr 
Channel address class did not offer bitwise
XOR and modulo operation. These two functions
where now added to the ChannelAddr class.

Change-Id: I02a5e49e9700cc5283415c921a25989a130e5d07
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39235
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-02-09 12:39:28 +00:00
Gabe Black
6e976fbb4b sim: Get rid of the IsConforming type trait template. 
The idea of this template was to distinguish types which should
grow/shrink based on the native size of the ABI in question. Or in other
words, if the ABI was 32 bit, the type should also be 32 bit, or 64 bit
and 64 bit.

Unfortunately, I had intended for Addr to be a conforming type (since
local pointers would be conforming), but uint64_t not to be. Since Addr
is defined as a typedef of uint64_t, the compiler would make *both*
types conforming, giving incorrect behavior on 32 bit systems.

Local pointers will need to be handled in a different way, likely with
the VPtr template, so that they will be treated correctly and not like
an explicitly 64 bit data type.

Change-Id: Idfdd5351260b48bb531a1926b93e0478a297826d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40495
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-02-09 00:36:00 +00:00
Gabe Black
0e0183f1d9 arch,sim: Use VPtr<> instead of Addr in system call signatures. 
This tells the GuestABI mechanism that these are guest pointers and not
uint64_ts, and that they should be treated as 32 bit or 64 bit values
depending on the size of pointers in the target ABI.

Change-Id: Ia9b5447848c52668a975d8b07b11ad457e756b13
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40498
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
 2021-02-09 00:35:39 +00:00
Giacomo Travaglini
1ea62dcf80 dev-arm: Reduce boilerplate when read/writing to Pio devices 
Change-Id: Id59ac950f37d7f4f2642daf324d501da1ee622de
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40775
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-02-08 14:54:39 +00:00
Daniel R. Carvalho
0a63e9ff0a dev: Fix register bank unit test in .debug 
The lack of definition of this static variable was throwing
and undefined reference error when running

  scons build/X86/unittests.opt.

For more info, check

  https://stackoverflow.com/questions/
    8016780/undefined-reference-to-static-constexpr-char

Change-Id: Id736dc42a82aea871da6a53c06d89fd399d3559a
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40836
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-02-07 13:07:14 +00:00
Daniel R. Carvalho
b75ff8fcff base: Fix storage unit test in .fast 
These tests depend on assertions being triggered, which
does not happen in .fast.

Change-Id: I0dd78f184809a453035046bc76640dfb5988bb5f
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40835
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-02-07 13:07:14 +00:00