cpu: Track flat register indices in the Minor CPU with a vector.

That avoids having to know the maximum number of dest registers there
can be in any instruction, and will likely not affect the performance of
the Minor CPU overall.

Change-Id: I4e49695ba06365d52eb4ce128d5cbb30db665bd7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38387
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

src/cpu/minor/decode.cc

@@ -182,9 +182,9 @@ Decode::evaluate()
                         static_inst->fetchMicroop(
                                 decode_info.microopPC.microPC());
 
-                    output_inst = new MinorDynInst(inst->id);
+                    output_inst =
+                        new MinorDynInst(static_micro_inst, inst->id);
                     output_inst->pc = decode_info.microopPC;
-                    output_inst->staticInst = static_micro_inst;
                     output_inst->fault = NoFault;
 
                     /* Allow a predicted next address only on the last

src/cpu/minor/dyn_inst.cc

@@ -79,7 +79,7 @@ void
 MinorDynInst::init()
 {
     if (!bubbleInst) {
-        bubbleInst = new MinorDynInst();
+        bubbleInst = new MinorDynInst(StaticInst::nullStaticInstPtr);
         assert(bubbleInst->isBubble());
         /* Make bubbleInst immortal */
         bubbleInst->incref();

src/cpu/minor/dyn_inst.hh

@@ -162,7 +162,7 @@ class MinorDynInst : public RefCounted
     static MinorDynInstPtr bubbleInst;
 
   public:
-    StaticInstPtr staticInst;
+    const StaticInstPtr staticInst;
 
     InstId id;
 
@@ -229,17 +229,18 @@ class MinorDynInst : public RefCounted
     /** Flat register indices so that, when clearing the scoreboard, we
      *  have the same register indices as when the instruction was marked
      *  up */
-    RegId flatDestRegIdx[TheISA::MaxInstDestRegs];
+    std::vector<RegId> flatDestRegIdx;
 
   public:
-    MinorDynInst(InstId id_ = InstId(), Fault fault_ = NoFault) :
-        staticInst(NULL), id(id_), traceData(NULL),
+    MinorDynInst(StaticInstPtr si, InstId id_=InstId(), Fault fault_=NoFault) :
+        staticInst(si), id(id_), traceData(NULL),
         pc(TheISA::PCState(0)), fault(fault_),
         triedToPredict(false), predictedTaken(false),
         fuIndex(0), inLSQ(false), translationFault(NoFault),
         inStoreBuffer(false), canEarlyIssue(false), predicate(true),
         memAccPredicate(true), instToWaitFor(0), extraCommitDelay(Cycles(0)),
-        extraCommitDelayExpr(NULL), minimumCommitCycle(Cycles(0))
+        extraCommitDelayExpr(NULL), minimumCommitCycle(Cycles(0)),
+        flatDestRegIdx(si ? si->numDestRegs() : 0)
     { }
 
   public:

src/cpu/minor/fetch2.cc

@@ -356,7 +356,8 @@ Fetch2::evaluate()
 
                 /* Make a new instruction and pick up the line, stream,
                  *  prediction, thread ids from the incoming line */
-                dyn_inst = new MinorDynInst(line_in->id);
+                dyn_inst = new MinorDynInst(
+                        StaticInst::nullStaticInstPtr, line_in->id);
 
                 /* Fetch and prediction sequence numbers originate here */
                 dyn_inst->id.fetchSeqNum = fetch_info.fetchSeqNum;
@@ -393,9 +394,15 @@ Fetch2::evaluate()
                  *  instructions longer than sizeof(MachInst) */
 
                 if (decoder->instReady()) {
+                    /* Note that the decoder can update the given PC.
+                     *  Remember not to assign it until *after* calling
+                     *  decode */
+                    StaticInstPtr decoded_inst =
+                        decoder->decode(fetch_info.pc);
+
                     /* Make a new instruction and pick up the line, stream,
                      *  prediction, thread ids from the incoming line */
-                    dyn_inst = new MinorDynInst(line_in->id);
+                    dyn_inst = new MinorDynInst(decoded_inst, line_in->id);
 
                     /* Fetch and prediction sequence numbers originate here */
                     dyn_inst->id.fetchSeqNum = fetch_info.fetchSeqNum;
@@ -404,12 +411,6 @@ Fetch2::evaluate()
                      *  has not been set */
                     assert(dyn_inst->id.execSeqNum == 0);
 
-                    /* Note that the decoder can update the given PC.
-                     *  Remember not to assign it until *after* calling
-                     *  decode */
-                    StaticInstPtr decoded_inst = decoder->decode(fetch_info.pc);
-                    dyn_inst->staticInst = decoded_inst;
-
                     dyn_inst->pc = fetch_info.pc;
                     DPRINTF(Fetch, "decoder inst %s\n", *dyn_inst);