derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arch-arm: Fix CPTR_EL2 writes

Browse Source 
* If E2H==1, CPTR_EL2.ZEN bits are not RES0.
* If E2H==1, CPTR_EL2.FPEN bits are not RES0.

Change-Id: Ic82b266975d89056d7c2f55464bd8a0c18a43e03
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39702
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2021-01-25 13:24:28 +00:00
parent 0bc0c0b9eb
commit be08e29991
1 changed files with 3 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/arch/arm/isa.cc
View File

@@ -936,6 +936,7 @@ ISA::setMiscReg(int misc_reg, RegVal val)
break;
case MISCREG_CPTR_EL2:
{
const HCR hcr = readMiscRegNoEffect(MISCREG_HCR_EL2);
const uint32_t ones = (uint32_t)(-1);
CPTR cptrMask = 0;
cptrMask.tcpac = ones;
@@ -943,7 +944,9 @@ ISA::setMiscReg(int misc_reg, RegVal val)
cptrMask.tfp = ones;
if (haveSVE) {
cptrMask.tz = ones;
cptrMask.zen = hcr.e2h ? ones : 0;
}
cptrMask.fpen = hcr.e2h ? ones : 0;
newVal &= cptrMask;
cptrMask = 0;
cptrMask.res1_13_12_el2 = ones;