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19 Commits

Author SHA1 Message Date
Matthew Poremba
53604aa483 arch-vega: Remove ASID parameter from Requests 
The ASID parameter was removed from the Request class header while the
Vega patches were under review and these were not updated.

Change-Id: Ie04027bac09a63063501a49ec438b69628972b2d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47101
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
 2021-06-24 13:57:42 +00:00
Matthew Poremba
3f8e979134 arch-vega: Simplify VecRegContainer in Vega 
VecRegContainer was simplified in [1] while the Vega patches were still
under review so the changes in [1] were not applied to arch-vega.

[1] https://gem5-review.googlesource.com/c/public/gem5/+/41995

Change-Id: I350ac94dc14e3ba0fb9619fa084e80cc8cbd7660
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47100
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-06-24 13:57:42 +00:00
Bobby R. Bruce
b372f3b6b7 arch-gcn3,python: Upgrade gpu_isa_parser.py to Python3 
Change-Id: I0a37809589d3796f7c74614a337cc690aae6c9a0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47021
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-06-22 20:05:27 +00:00
Bobby R. Bruce
9bc66c5400 arch-gcn3,python: Fix incorrect syntax in ast_interpreter.py 
Includes upgrading prints to Python3.

Change-Id: I3349fa6220ad7577b4b4ab9231fb48a8ac4be6fb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47020
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-06-22 20:05:27 +00:00
Daniel R. Carvalho
4dd099ba3d misc: Rename Enums namespace as enums 
As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::Enums became ::enums.

Change-Id: I39b5fb48817ad16abbac92f6254284b37fc90c40
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45420
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-05-29 11:13:49 +00:00
Matthew Poremba
aa19af29ad arch-vega,arch-gcn3: Fix s_cmp_lt_u32 
Was using less-than-or-equal rather than less-than. All other comparison
instructions look correct otherwise.

Change-Id: Iee0374554f21a80a6da2eb75f38b22c83b6e1e9c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45499
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-05-14 07:56:17 +00:00
Gabe Black
669d2c48f2 arch,mem: Use szext instead of sext as appropriate. 
When the value being passed to sext needs to be masked first, szext can
be used instead without the masking.

Change-Id: I98c99ad2731216fe8ccf1253f5ac3891fe03b1de
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42386
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-04-20 00:12:25 +00:00
Giacomo Travaglini
dabb0c8f45 misc: Replace std::conditional with std::conditional_t 
Change-Id: I50d26d958d521c30b69d31426380b1e2e213a9e6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44506
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-04-15 08:15:45 +00:00
Gabe Black
0dade68dae arch,cpu,gpu-compute: Further simplify VecRegContainer. 
Get rid of VecRegT, and a few redundant or unused methods.

Change-Id: I6c88c40653e1939fe74b8ffb847ef50ab8064670
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41995
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-04-10 07:31:23 +00:00
Kyle Roarty
49f7565904 arch-vega: Update FLAT instructions to use offset 
In Vega, flat instructions use an offset when
computing the address (section 9.4 of chapter 9
'Flat Memory Instructions' in Vega ISA manual).
This is different from the GCN3 baseline.

Change-Id: I9fe36f028014889ef566055458c451442403a289
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42213
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
 2021-04-01 02:58:31 +00:00
Kyle Roarty
2bb8d6bc0c gpu-compute: remove index-based operand access 
This commit removes functions that indexed into the
vectors that held the operands. Instead, for-each loops
are used, iterating through one of 6 vectors
(src, dst, srcScalar, srcVec, dstScalar, dstVec)
that all hold various (potentially overlapping)
combinations of the operands.

Change-Id: Ia3a857c8f6675be86c51ba2f77e3d85bfea9ffdb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42212
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
 2021-04-01 02:58:31 +00:00
Kyle Roarty
b40b361bee arch-vega, gpu-compute: Add vectors to hold op info 
This removes the need for redundant functions like
isScalarRegister/isVectorRegister, as well as
isSrcOperand/isDstOperand. Also, the op info is only
generated once this way instead of every time it's needed.

Change-Id: I8af5080502ed08ed9107a441e2728828f86496f4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42211
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
 2021-04-01 02:58:31 +00:00
Tony Gutierrez
0e2564a629 arch-gcn3, gpu-compute: Update getRegisterIndex() API 
This change removes the GPUDynInstPtr argument from
getRegisterIndex(). The dynamic inst was only needed
to get access to its parent WF's state so it could
determine the number of scalar registers the wave was
allocated. However, we can simply pass the number of
scalar registers directly. This cuts down on shared
pointer usage.

Change-Id: I29ab8d9a3de1f8b82b820ef421fc653284567c65
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42210
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
 2021-04-01 02:58:31 +00:00
Kyle Roarty
9ddfe09649 arch-vega: Add Vega-specific opcodes 
The opcodes aren't implemented yet, returning nullptr

Change-Id: I700c2158035aea84e6365a32d53304accab59d96
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42208
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
 2021-04-01 02:58:31 +00:00
Kyle Roarty
f85a861594 arch-vega: Order pointer functions by opcode 
This makes it easier to add new ops

Change-Id: I2820005c42c87a1289aa87ddcdc5473ff0e57bd9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42207
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
 2021-04-01 02:58:31 +00:00
Kyle Roarty
16548557ef arch-vega: Add decodings for Flat, Global, Scratch 
Does not implement the functions yet

Change-Id: I32feab747b13bd2eff98983e3281c0d82e756221
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42206
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
 2021-04-01 02:58:31 +00:00
Kyle Roarty
b30e9645d7 arch-vega: Update instruction encodings 
This also renames VOP3 and VOP3_SDST_ENC to
VOP3A and VOP3B, matching the ISA.

Change-Id: I56f254433b1f3181d4ee6896f957a2256e3c7b29
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42205
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
 2021-04-01 02:58:31 +00:00
Kyle Roarty
f7d4ff6ef5 arch-vega: Add Vega ISA as a copy of GCN3 
This changeset adds Vega support as a copy of GCN3.
Configs have been modified to include both ISAs.
Current implementation is not complete and needs
modifications to fully comply with the ISA manual:

https://developer.amd.com/wp-content/resources/
Vega_Shader_ISA_28July2017.pdf

Change-Id: I608aa6747a45594f8e1bd7802da1883cf612168b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42204
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
 2021-04-01 02:58:31 +00:00
Kyle Roarty
de134bae21 arch-gcn3: Modify directory structure as prep for adding vega isa 
Change-Id: I7c5f4a3a9d82ca4550e833dec2cd576dbe333627
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42203
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
 2021-03-29 21:21:35 +00:00