configs, dev, learning-gem5, python, tests: more clarification

This commit contains the rest of the base 2 vs base 10 cache/memory
size clarifications. It also changes the warning message to use
warn(). With these changes, the warning message should now no
longer show up during a fresh compilation of gem5.

Change-Id: Ia63f841bdf045b76473437f41548fab27dc19631

configs/example/gem5_library/arm-hello.py

@@ -59,12 +59,12 @@ requires(isa_required=ISA.ARM)
 cache_hierarchy = NoCache()
 
 # We use a single channel DDR3_1600 memory system
-memory = SingleChannelDDR3_1600(size="32MB")
+memory = SingleChannelDDR3_1600(size="32MiB")
 
 # We use a simple Timing processor with one core.
 processor = SimpleProcessor(cpu_type=CPUTypes.TIMING, isa=ISA.ARM, num_cores=1)
 
-# The gem5 library simble board which can be used to run simple SE-mode
+# The gem5 library simple board which can be used to run simple SE-mode
 # simulations.
 board = SimpleBoard(
     clk_freq="3GHz",

configs/example/gem5_library/arm-ubuntu-run-with-kvm.py

@@ -67,11 +67,11 @@ from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierar
 
 # Here we setup the parameters of the l1 and l2 caches.
 cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
-    l1d_size="16kB", l1i_size="16kB", l2_size="256kB"
+    l1d_size="16KiB", l1i_size="16KiB", l2_size="256KiB"
 )
 
 # Memory: Dual Channel DDR4 2400 DRAM device.
-memory = DualChannelDDR4_2400(size="2GB")
+memory = DualChannelDDR4_2400(size="2GiB")
 
 # Here we setup the processor. This is a special switchable processor in which
 # a starting core type and a switch core type must be specified. Once a

configs/example/gem5_library/arm-ubuntu-run.py

@@ -66,12 +66,12 @@ from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierar
 
 # Here we setup the parameters of the l1 and l2 caches.
 cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
-    l1d_size="16kB", l1i_size="16kB", l2_size="256kB"
+    l1d_size="16KiB", l1i_size="16KiB", l2_size="256KiB"
 )
 
 # Memory: Dual Channel DDR4 2400 DRAM device.
 
-memory = DualChannelDDR4_2400(size="2GB")
+memory = DualChannelDDR4_2400(size="2GiB")
 
 # Here we setup the processor. We use a simple TIMING processor. The config
 # script was also tested with ATOMIC processor.

configs/example/gem5_library/caches/octopi-cache-example.py

@@ -75,7 +75,7 @@ cache_hierarchy = OctopiCache(
     is_fullsystem=True,
 )
 
-memory = DualChannelDDR4_2400(size="16GB")
+memory = DualChannelDDR4_2400(size="16GiB")
 
 # The number of cores must be consistent with
 # num_core_complexes and num_cores_per_core_complexes

configs/example/gem5_library/checkpoints/riscv-hello-restore-checkpoint.py

@@ -64,14 +64,14 @@ requires(isa_required=ISA.RISCV)
 cache_hierarchy = NoCache()
 
 # We use a single channel DDR3_1600 memory system
-memory = SingleChannelDDR3_1600(size="32MB")
+memory = SingleChannelDDR3_1600(size="32MiB")
 
 # We use a simple Timing processor with one core.
 processor = SimpleProcessor(
     cpu_type=CPUTypes.TIMING, isa=ISA.RISCV, num_cores=1
 )
 
-# The gem5 library simble board which can be used to run simple SE-mode
+# The gem5 library simple board which can be used to run simple SE-mode
 # simulations.
 board = SimpleBoard(
     clk_freq="3GHz",

configs/example/gem5_library/checkpoints/riscv-hello-save-checkpoint.py

@@ -75,14 +75,14 @@ requires(isa_required=ISA.RISCV)
 cache_hierarchy = NoCache()
 
 # We use a single channel DDR3_1600 memory system
-memory = SingleChannelDDR3_1600(size="32MB")
+memory = SingleChannelDDR3_1600(size="32MiB")
 
 # We use a simple Timing processor with one core.
 processor = SimpleProcessor(
     cpu_type=CPUTypes.TIMING, isa=ISA.RISCV, num_cores=1
 )
 
-# The gem5 library simble board which can be used to run simple SE-mode
+# The gem5 library simple board which can be used to run simple SE-mode
 # simulations.
 board = SimpleBoard(
     clk_freq="3GHz",

configs/example/gem5_library/checkpoints/simpoints-se-checkpoint.py

@@ -94,7 +94,7 @@ cache_hierarchy = NoCache()
 # Using simple memory to take checkpoints might slightly imporve the
 # performance in atomic mode. The memory structure can be changed when
 # restoring from a checkpoint, but the size of the memory must be maintained.
-memory = SingleChannelDDR3_1600(size="2GB")
+memory = SingleChannelDDR3_1600(size="2GiB")
 
 processor = SimpleProcessor(
     cpu_type=CPUTypes.ATOMIC,

configs/example/gem5_library/checkpoints/simpoints-se-restore.py

@@ -81,14 +81,14 @@ requires(isa_required=ISA.X86)
 # The cache hierarchy can be different from the cache hierarchy used in taking
 # the checkpoints
 cache_hierarchy = PrivateL1PrivateL2WalkCacheHierarchy(
-    l1d_size="32kB",
-    l1i_size="32kB",
-    l2_size="256kB",
+    l1d_size="32KiB",
+    l1i_size="32KiB",
+    l2_size="256KiB",
 )
 
 # The memory structure can be different from the memory structure used in
 # taking the checkpoints, but the size of the memory must be maintained
-memory = DualChannelDDR4_2400(size="2GB")
+memory = DualChannelDDR4_2400(size="2GiB")
 
 processor = SimpleProcessor(
     cpu_type=CPUTypes.TIMING,

configs/example/gem5_library/dramsys/arm-hello-dramsys.py

@@ -50,7 +50,7 @@ from gem5.utils.requires import requires
 requires(isa_required=ISA.ARM)
 
 # We need a cache as DRAMSys only accepts requests with the size of a cache line
-cache_hierarchy = PrivateL1CacheHierarchy(l1d_size="32kB", l1i_size="32kB")
+cache_hierarchy = PrivateL1CacheHierarchy(l1d_size="32KiB", l1i_size="32KiB")
 
 # We use a single channel DDR3_1600 memory system
 memory = DRAMSysDDR3_1600(recordable=True)
@@ -58,7 +58,7 @@ memory = DRAMSysDDR3_1600(recordable=True)
 # We use a simple Timing processor with one core.
 processor = SimpleProcessor(cpu_type=CPUTypes.TIMING, isa=ISA.ARM, num_cores=1)
 
-# The gem5 library simble board which can be used to run simple SE-mode
+# The gem5 library simple board which can be used to run simple SE-mode
 # simulations.
 board = SimpleBoard(
     clk_freq="3GHz",

configs/example/gem5_library/dramsys/dramsys-traffic.py

@@ -40,12 +40,12 @@ from gem5.simulate.simulator import Simulator
 memory = DRAMSysMem(
     configuration="ext/dramsys/DRAMSys/configs/ddr4-example.json",
     recordable=True,
-    size="4GB",
+    size="4GiB",
 )
 
 generator = LinearGenerator(
     duration="250us",
-    rate="40GB/s",
+    rate="40GiB/s",
     num_cores=1,
     max_addr=memory.get_size(),
 )

configs/example/gem5_library/looppoints/create-looppoint-checkpoints.py

@@ -94,7 +94,7 @@ cache_hierarchy = NoCache()
 # performance in atomic mode. The memory structure can be changed when
 # restoring from a checkpoint, but the size of the memory must be equal or
 # greater to that taken when creating the checkpoint.
-memory = SingleChannelDDR3_1600(size="2GB")
+memory = SingleChannelDDR3_1600(size="2GiB")
 
 processor = SimpleProcessor(
     cpu_type=CPUTypes.ATOMIC,

configs/example/gem5_library/looppoints/restore-looppoint-checkpoint.py

@@ -91,14 +91,14 @@ args = parser.parse_args()
 # The cache hierarchy can be different from the cache hierarchy used in taking
 # the checkpoints
 cache_hierarchy = PrivateL1PrivateL2WalkCacheHierarchy(
-    l1d_size="32kB",
-    l1i_size="32kB",
-    l2_size="256kB",
+    l1d_size="32KiB",
+    l1i_size="32KiB",
+    l2_size="256KiB",
 )
 
 # The memory structure can be different from the memory structure used in
 # taking the checkpoints, but the size of the memory must be equal or larger.
-memory = DualChannelDDR4_2400(size="2GB")
+memory = DualChannelDDR4_2400(size="2GiB")
 
 processor = SimpleProcessor(
     cpu_type=CPUTypes.TIMING,

configs/example/gem5_library/multisim/multisim-fs-x86-npb.py

@@ -101,15 +101,15 @@ multisim.set_num_processes(3)
 for benchmark in obtain_resource("npb-benchmark-suite"):
     for num_cores in [1, 2]:
         cache_hierarchy = MESITwoLevelCacheHierarchy(
-            l1d_size="32kB",
-            l1i_size="32kB",
-            l2_size="256kB",
+            l1d_size="32KiB",
+            l1i_size="32KiB",
+            l2_size="256KiB",
             l1d_assoc=8,
             l1i_assoc=8,
             l2_assoc=16,
             num_l2_banks=2,
         )
-        memory = DualChannelDDR4_2400(size="3GB")
+        memory = DualChannelDDR4_2400(size="3GiB")
         processor = SimpleSwitchableProcessor(
             starting_core_type=CPUTypes.ATOMIC,
             switch_core_type=CPUTypes.TIMING,

configs/example/gem5_library/multisim/multisim-print-this.py

@@ -70,7 +70,7 @@ multisim.set_num_processes(2)
 
 for process_id in range(5):
     cache_hierarchy = NoCache()
-    memory = SingleChannelDDR3_1600(size="32MB")
+    memory = SingleChannelDDR3_1600(size="32MiB")
     processor = SimpleProcessor(
         cpu_type=CPUTypes.TIMING, isa=ISA.X86, num_cores=1
     )

configs/example/gem5_library/power-hello.py

@@ -59,7 +59,7 @@ requires(isa_required=ISA.POWER)
 cache_hierarchy = NoCache()
 
 # We use a single channel DDR4_2400 memory system
-memory = SingleChannelDDR4_2400(size="32MB")
+memory = SingleChannelDDR4_2400(size="32MiB")
 
 # We use a simple ATOMIC processor with one core.
 processor = SimpleProcessor(

configs/example/gem5_library/riscv-ubuntu-run.py

@@ -63,12 +63,12 @@ from gem5.components.cachehierarchies.classic.private_l1_private_l2_walk_cache_h
 
 # Here we setup the parameters of the l1 and l2 caches.
 cache_hierarchy = PrivateL1PrivateL2WalkCacheHierarchy(
-    l1d_size="16kB", l1i_size="16kB", l2_size="256kB"
+    l1d_size="16KiB", l1i_size="16KiB", l2_size="256KiB"
 )
 
 # Memory: Dual Channel DDR4 2400 DRAM device.
 
-memory = DualChannelDDR4_2400(size="3GB")
+memory = DualChannelDDR4_2400(size="3GiB")
 
 # Here we setup the processor. We use a simple processor.
 processor = SimpleProcessor(

configs/example/gem5_library/riscvmatched-fs.py

@@ -64,7 +64,7 @@ args = parser.parse_args()
 # instantiate the riscv matched board with default parameters
 board = RISCVMatchedBoard(
     clk_freq="1.2GHz",
-    l2_size="2MB",
+    l2_size="2MiB",
     is_fs=True,
 )
 

configs/example/gem5_library/x86-gapbs-benchmarks.py

@@ -28,7 +28,7 @@
 Script to run GAPBS benchmarks with gem5. The script expects the
 benchmark program and the simulation size to run. The input is in the format
 <benchmark_prog> <size> <synthetic>
-The system is fixed with 2 CPU cores, MESI Two Level system cache and 3 GB
+The system is fixed with 2 CPU cores, MESI Two Level system cache and 3 GiB
 DDR4 memory. It uses the x86 board.
 
 This script will count the total number of instructions executed
@@ -102,18 +102,18 @@ from gem5.components.cachehierarchies.ruby.mesi_two_level_cache_hierarchy import
 )
 
 cache_hierarchy = MESITwoLevelCacheHierarchy(
-    l1d_size="32kB",
+    l1d_size="32KiB",
     l1d_assoc=8,
-    l1i_size="32kB",
+    l1i_size="32KiB",
     l1i_assoc=8,
-    l2_size="256kB",
+    l2_size="256KiB",
     l2_assoc=16,
     num_l2_banks=2,
 )
 # Memory: Dual Channel DDR4 2400 DRAM device.
-# The X86 board only supports 3 GB of main memory.
+# The X86 board only supports 3 GiB of main memory.
 
-memory = DualChannelDDR4_2400(size="3GB")
+memory = DualChannelDDR4_2400(size="3GiB")
 
 # Here we setup the processor. This is a special switchable processor in which
 # a starting core type and a switch core type must be specified. Once a

configs/example/gem5_library/x86-npb-benchmarks.py

@@ -28,7 +28,7 @@
 Script to run NAS parallel benchmarks with gem5. The script expects the
 benchmark program to run. The input is in the format
 <benchmark_prog>.<class>.x .The system is fixed with 2 CPU cores, MESI
-Two Level system cache and 3 GB DDR4 memory. It uses the x86 board.
+Two Level system cache and 3 GiB DDR4 memory. It uses the x86 board.
 
 This script will count the total number of instructions executed
 in the ROI. It also tracks how much wallclock and simulated time.
@@ -77,8 +77,8 @@ requires(
 # Following are the list of benchmark programs for npb.
 
 # We are restricting classes of NPB to A, B and C as the other classes (D and
-# F) require main memory size of more than 3 GB. The X86Board is currently
-# limited to 3 GB of memory. This limitation is explained later in line 136.
+# F) require main memory size of more than 3 GiB. The X86Board is currently
+# limited to 3 GiB of memory. This limitation is explained later in line 136.
 
 # The resource disk has binaries for class D. However, only `ep` benchmark
 # works with class D in the current configuration. More information on the
@@ -109,13 +109,13 @@ parser.add_argument(
 args = parser.parse_args()
 
 
-# The simulation may fail in the case of `mg` with class C as it uses 3.3 GB
+# The simulation may fail in the case of `mg` with class C as it uses 3.3 GiB
 # of memory (more information is available at https://arxiv.org/abs/2010.13216).
 # We warn the user here.
 
 if args.benchmark == "npb-mg-c":
     warn(
-        "mg.C uses 3.3 GB of memory. Currently we are simulating 3 GB\
+        "mg.C uses 3.3 GiB of memory. Currently we are simulating 3 GiB\
     of main memory in the system."
     )
 
@@ -124,7 +124,7 @@ if args.benchmark == "npb-mg-c":
 elif args.benchmark == "npb-ft-c":
     warn(
         "There is not enough memory for ft.C. Currently we are\
-    simulating 3 GB of main memory in the system."
+    simulating 3 GiB of main memory in the system."
     )
 
 # Checking for the maximum number of instructions, if provided by the user.
@@ -137,18 +137,18 @@ from gem5.components.cachehierarchies.ruby.mesi_two_level_cache_hierarchy import
 )
 
 cache_hierarchy = MESITwoLevelCacheHierarchy(
-    l1d_size="32kB",
+    l1d_size="32KiB",
     l1d_assoc=8,
-    l1i_size="32kB",
+    l1i_size="32KiB",
     l1i_assoc=8,
-    l2_size="256kB",
+    l2_size="256KiB",
     l2_assoc=16,
     num_l2_banks=2,
 )
 # Memory: Dual Channel DDR4 2400 DRAM device.
-# The X86 board only supports 3 GB of main memory.
+# The X86 board only supports 3 GiB of main memory.
 
-memory = DualChannelDDR4_2400(size="3GB")
+memory = DualChannelDDR4_2400(size="3GiB")
 
 # Here we setup the processor. This is a special switchable processor in which
 # a starting core type and a switch core type must be specified. Once a

configs/example/gem5_library/x86-parsec-benchmarks.py

@@ -28,7 +28,7 @@
 Script to run PARSEC benchmarks with gem5.
 The script expects a benchmark program name and the simulation
 size. The system is fixed with 2 CPU cores, MESI Two Level system
-cache and 3 GB DDR4 memory. It uses the x86 board.
+cache and 3 GiB DDR4 memory. It uses the x86 board.
 
 This script will count the total number of instructions executed
 in the ROI. It also tracks how much wallclock and simulated time.
@@ -124,19 +124,19 @@ from gem5.components.cachehierarchies.ruby.mesi_two_level_cache_hierarchy import
 )
 
 cache_hierarchy = MESITwoLevelCacheHierarchy(
-    l1d_size="32kB",
+    l1d_size="32KiB",
     l1d_assoc=8,
-    l1i_size="32kB",
+    l1i_size="32KiB",
     l1i_assoc=8,
-    l2_size="256kB",
+    l2_size="256KiB",
     l2_assoc=16,
     num_l2_banks=2,
 )
 
 # Memory: Dual Channel DDR4 2400 DRAM device.
-# The X86 board only supports 3 GB of main memory.
+# The X86 board only supports 3 GiB of main memory.
 
-memory = DualChannelDDR4_2400(size="3GB")
+memory = DualChannelDDR4_2400(size="3GiB")
 
 # Here we setup the processor. This is a special switchable processor in which
 # a starting core type and a switch core type must be specified. Once a

configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py

@@ -28,7 +28,7 @@
 Script to run SPEC CPU2006 benchmarks with gem5.
 The script expects a benchmark program name and the simulation
 size. The system is fixed with 2 CPU cores, MESI Two Level system
-cache and 3 GB DDR4 memory. It uses the x86 board.
+cache and 3 GiB DDR4 memory. It uses the x86 board.
 
 This script will count the total number of instructions executed
 in the ROI. It also tracks how much wallclock and simulated time.
@@ -193,18 +193,18 @@ from gem5.components.cachehierarchies.ruby.mesi_two_level_cache_hierarchy import
 )
 
 cache_hierarchy = MESITwoLevelCacheHierarchy(
-    l1d_size="32kB",
+    l1d_size="32KiB",
     l1d_assoc=8,
-    l1i_size="32kB",
+    l1i_size="32KiB",
     l1i_assoc=8,
-    l2_size="256kB",
+    l2_size="256KiB",
     l2_assoc=16,
     num_l2_banks=2,
 )
 # Memory: Dual Channel DDR4 2400 DRAM device.
-# The X86 board only supports 3 GB of main memory.
+# The X86 board only supports 3 GiB of main memory.
 
-memory = DualChannelDDR4_2400(size="3GB")
+memory = DualChannelDDR4_2400(size="3GiB")
 
 # Here we setup the processor. This is a special switchable processor in which
 # a starting core type and a switch core type must be specified. Once a

configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py

@@ -28,7 +28,7 @@
 Script to run SPEC CPU2017 benchmarks with gem5.
 The script expects a benchmark program name and the simulation
 size. The system is fixed with 2 CPU cores, MESI Two Level system
-cache and 3 GB DDR4 memory. It uses the x86 board.
+cache and 3 GiB DDR4 memory. It uses the x86 board.
 
 This script will count the total number of instructions executed
 in the ROI. It also tracks how much wallclock and simulated time.
@@ -207,18 +207,18 @@ from gem5.components.cachehierarchies.ruby.mesi_two_level_cache_hierarchy import
 )
 
 cache_hierarchy = MESITwoLevelCacheHierarchy(
-    l1d_size="32kB",
+    l1d_size="32KiB",
     l1d_assoc=8,
-    l1i_size="32kB",
+    l1i_size="32KiB",
     l1i_assoc=8,
-    l2_size="256kB",
+    l2_size="256KiB",
     l2_assoc=16,
     num_l2_banks=2,
 )
 # Memory: Dual Channel DDR4 2400 DRAM device.
-# The X86 board only supports 3 GB of main memory.
+# The X86 board only supports 3 GiB of main memory.
 
-memory = DualChannelDDR4_2400(size="3GB")
+memory = DualChannelDDR4_2400(size="3GiB")
 
 # Here we setup the processor. This is a special switchable processor in which
 # a starting core type and a switch core type must be specified. Once a

configs/example/gem5_library/x86-ubuntu-run-with-kvm.py

@@ -67,17 +67,17 @@ from gem5.components.cachehierarchies.ruby.mesi_two_level_cache_hierarchy import
 
 # Here we setup a MESI Two Level Cache Hierarchy.
 cache_hierarchy = MESITwoLevelCacheHierarchy(
-    l1d_size="16kB",
+    l1d_size="16KiB",
     l1d_assoc=8,
-    l1i_size="16kB",
+    l1i_size="16KiB",
     l1i_assoc=8,
-    l2_size="256kB",
+    l2_size="256KiB",
     l2_assoc=16,
     num_l2_banks=1,
 )
 
 # Setup the system memory.
-memory = SingleChannelDDR3_1600(size="3GB")
+memory = SingleChannelDDR3_1600(size="3GiB")
 
 # Here we setup the processor. This is a special switchable processor in which
 # a starting core type and a switch core type must be specified. Once a