e1db67c4bd
This commit contains the rest of the base 2 vs base 10 cache/memory size clarifications. It also changes the warning message to use warn(). With these changes, the warning message should now no longer show up during a fresh compilation of gem5. Change-Id: Ia63f841bdf045b76473437f41548fab27dc19631
97 lines
3.6 KiB
Python
97 lines
3.6 KiB
Python
# Copyright (c) 2021 The Regents of the University of California
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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"""
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This script shows an example of running a full system RISCV Ubuntu boot
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simulation using the gem5 library. This simulation boots Ubuntu 20.04 using
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2 TIMING CPU cores. The simulation ends when the startup is completed
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successfully.
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Usage
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-----
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```
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scons build/RISCV/gem5.opt
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./build/RISCV/gem5.opt \
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configs/example/gem5_library/riscv-ubuntu-run.py
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```
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"""
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import m5
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from m5.objects import Root
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from gem5.components.boards.riscv_board import RiscvBoard
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from gem5.components.memory import DualChannelDDR4_2400
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from gem5.components.processors.cpu_types import CPUTypes
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from gem5.components.processors.simple_processor import SimpleProcessor
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from gem5.isas import ISA
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from gem5.resources.resource import obtain_resource
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from gem5.simulate.simulator import Simulator
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from gem5.utils.requires import requires
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# This runs a check to ensure the gem5 binary is compiled for RISCV.
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requires(isa_required=ISA.RISCV)
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# With RISCV, we use simple caches.
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from gem5.components.cachehierarchies.classic.private_l1_private_l2_walk_cache_hierarchy import (
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PrivateL1PrivateL2WalkCacheHierarchy,
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)
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# Here we setup the parameters of the l1 and l2 caches.
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cache_hierarchy = PrivateL1PrivateL2WalkCacheHierarchy(
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l1d_size="16KiB", l1i_size="16KiB", l2_size="256KiB"
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)
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# Memory: Dual Channel DDR4 2400 DRAM device.
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memory = DualChannelDDR4_2400(size="3GiB")
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# Here we setup the processor. We use a simple processor.
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processor = SimpleProcessor(
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cpu_type=CPUTypes.TIMING, isa=ISA.RISCV, num_cores=2
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)
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# Here we setup the board. The RiscvBoard allows for Full-System RISCV
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# simulations.
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board = RiscvBoard(
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clk_freq="3GHz",
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processor=processor,
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memory=memory,
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cache_hierarchy=cache_hierarchy,
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)
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# Here we a full system workload: "riscv-ubuntu-20.04-boot" which boots
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# Ubuntu 20.04. Once the system successfully boots it encounters an `m5_exit`
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# instruction which stops the simulation. When the simulation has ended you may
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# inspect `m5out/system.pc.com_1.device` to see the stdout.
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board.set_workload(
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obtain_resource("riscv-ubuntu-20.04-boot", resource_version="3.0.0")
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)
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simulator = Simulator(board=board)
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simulator.run()
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