e1db67c4bd
This commit contains the rest of the base 2 vs base 10 cache/memory size clarifications. It also changes the warning message to use warn(). With these changes, the warning message should now no longer show up during a fresh compilation of gem5. Change-Id: Ia63f841bdf045b76473437f41548fab27dc19631
106 lines
3.5 KiB
Python
106 lines
3.5 KiB
Python
# Copyright (c) 2023 The Regents of the University of California
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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"""
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This script boots Ubuntu 20.04 with 8 timing cores in 1 CCD.
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Usage
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-----
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```
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scons build/ARM_MESI_Three_Level/gem5.opt -j `nproc`
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./build/ARM_MESI_Three_Level/gem5.opt \
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configs/example/gem5_library/caches/octopi-cache-example.py
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```
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"""
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from m5.objects import (
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ArmDefaultRelease,
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VExpress_GEM5_Foundation,
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)
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from gem5.coherence_protocol import CoherenceProtocol
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from gem5.components.boards.arm_board import ArmBoard
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from gem5.components.cachehierarchies.ruby.caches.mesi_three_level.octopi import (
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OctopiCache,
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)
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from gem5.components.memory import DualChannelDDR4_2400
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from gem5.components.processors.cpu_types import CPUTypes
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from gem5.components.processors.simple_processor import SimpleProcessor
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from gem5.isas import ISA
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from gem5.resources.resource import obtain_resource
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from gem5.simulate.simulator import Simulator
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from gem5.utils.requires import requires
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num_ccds = 1 # CCDs
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num_cores_per_ccd = 8 # 8 cores/CCD
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# OctopiCache is built on top of gem5's MESI_Three_Level cache coherence
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# protocol
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requires(coherence_protocol_required=CoherenceProtocol.MESI_THREE_LEVEL)
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cache_hierarchy = OctopiCache(
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l1i_size="32KiB",
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l1i_assoc=8,
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l1d_size="32KiB",
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l1d_assoc=8,
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l2_size="512KiB",
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l2_assoc=8,
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l3_size="32MiB",
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l3_assoc=16,
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num_core_complexes=num_ccds,
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is_fullsystem=True,
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)
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memory = DualChannelDDR4_2400(size="16GiB")
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# The number of cores must be consistent with
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# num_core_complexes and num_cores_per_core_complexes
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processor = SimpleProcessor(
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cpu_type=CPUTypes.TIMING,
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isa=ISA.ARM,
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num_cores=num_ccds * num_cores_per_ccd,
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)
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release = ArmDefaultRelease()
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platform = VExpress_GEM5_Foundation()
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board = ArmBoard(
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clk_freq="4GHz",
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processor=processor,
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memory=memory,
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cache_hierarchy=cache_hierarchy,
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release=release,
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platform=platform,
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)
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board.set_workload(
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obtain_resource("arm64-ubuntu-20.04-boot", resource_version="2.0.0")
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)
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simulator = Simulator(board=board)
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simulator.run()
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