sim: Remove the byte_order parameter from System.

Instead, get the byte order from the workload. The workload has a better
idea what the byte order should be, for instance based on what software
it's loaded or how the hardware was configured, and this gets rid of a
use of TARGET_ISA which was setting a default endianness.

Change-Id: Ic5d8a6f69a664957c4f837e3799ff93397ccfc64
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52106
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

src/sim/System.py

@@ -49,11 +49,6 @@ from m5.objects.Workload import StubWorkload
 class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing',
                                 'atomic_noncaching']
 
-if buildEnv['TARGET_ISA'] in ('sparc', 'power'):
-    default_byte_order = 'big'
-else:
-    default_byte_order = 'little'
-
 class System(SimObject):
     type = 'System'
     cxx_header = "sim/system.hh"
@@ -96,9 +91,6 @@ class System(SimObject):
 
     cache_line_size = Param.Unsigned(64, "Cache line size in bytes")
 
-    byte_order = Param.ByteOrder(default_byte_order,
-                                 "Default byte order of system components")
-
     redirect_paths = VectorParam.RedirectPath([], "Path redirections")
 
     exit_on_work_items = Param.Bool(False, "Exit from the simulation loop when "

src/sim/system.hh

@@ -388,7 +388,7 @@ class System : public SimObject, public PCEventScope
     ByteOrder
     getGuestByteOrder() const
     {
-        return params().byte_order;
+        return workload->byteOrder();
     }
 
     /**