From bf5be72804365fb7679cf7075efad9c7699389f6 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 27 Oct 2021 01:23:30 -0700 Subject: [PATCH] sim: Remove the byte_order parameter from System. Instead, get the byte order from the workload. The workload has a better idea what the byte order should be, for instance based on what software it's loaded or how the hardware was configured, and this gets rid of a use of TARGET_ISA which was setting a default endianness. Change-Id: Ic5d8a6f69a664957c4f837e3799ff93397ccfc64 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52106 Tested-by: kokoro Maintainer: Gabe Black Reviewed-by: Andreas Sandberg --- src/sim/System.py | 8 -------- src/sim/system.hh | 2 +- 2 files changed, 1 insertion(+), 9 deletions(-) diff --git a/src/sim/System.py b/src/sim/System.py index 115fb94f23..596e25cc70 100644 --- a/src/sim/System.py +++ b/src/sim/System.py @@ -49,11 +49,6 @@ from m5.objects.Workload import StubWorkload class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing', 'atomic_noncaching'] -if buildEnv['TARGET_ISA'] in ('sparc', 'power'): - default_byte_order = 'big' -else: - default_byte_order = 'little' - class System(SimObject): type = 'System' cxx_header = "sim/system.hh" @@ -96,9 +91,6 @@ class System(SimObject): cache_line_size = Param.Unsigned(64, "Cache line size in bytes") - byte_order = Param.ByteOrder(default_byte_order, - "Default byte order of system components") - redirect_paths = VectorParam.RedirectPath([], "Path redirections") exit_on_work_items = Param.Bool(False, "Exit from the simulation loop when " diff --git a/src/sim/system.hh b/src/sim/system.hh index 7aeeea7a5d..8f09b96c7e 100644 --- a/src/sim/system.hh +++ b/src/sim/system.hh @@ -388,7 +388,7 @@ class System : public SimObject, public PCEventScope ByteOrder getGuestByteOrder() const { - return params().byte_order; + return workload->byteOrder(); } /**