diff --git a/src/sim/System.py b/src/sim/System.py
index 115fb94f23..596e25cc70 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -49,11 +49,6 @@ from m5.objects.Workload import StubWorkload
 class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing',
                                 'atomic_noncaching']
 
-if buildEnv['TARGET_ISA'] in ('sparc', 'power'):
-    default_byte_order = 'big'
-else:
-    default_byte_order = 'little'
-
 class System(SimObject):
     type = 'System'
     cxx_header = "sim/system.hh"
@@ -96,9 +91,6 @@ class System(SimObject):
 
     cache_line_size = Param.Unsigned(64, "Cache line size in bytes")
 
-    byte_order = Param.ByteOrder(default_byte_order,
-                                 "Default byte order of system components")
-
     redirect_paths = VectorParam.RedirectPath([], "Path redirections")
 
     exit_on_work_items = Param.Bool(False, "Exit from the simulation loop when "
diff --git a/src/sim/system.hh b/src/sim/system.hh
index 7aeeea7a5d..8f09b96c7e 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -388,7 +388,7 @@ class System : public SimObject, public PCEventScope
     ByteOrder
     getGuestByteOrder() const
     {
-        return params().byte_order;
+        return workload->byteOrder();
     }
 
     /**