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python: Add has_dma_ports check to mesi_two_level

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Previously the MesiTwoLevelCacheHierarchy assumed the board had dma
ports. This change adds a simple check and skips adding the
DMASequencers if the board does not have any.

Change-Id: I64ee68267d16c9d9a6096ba7fd660f04515b2b3c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49929
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
This commit is contained in:
Bobby R. Bruce
2021-09-03 12:23:29 -07:00
parent 752394b243
commit 958029328f
1 changed files with 7 additions and 6 deletions
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13
src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
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@@ -169,13 +169,14 @@ class MESITwoLevelCacheHierarchy(
for dir in self._directory_controllers:
dir.ruby_system = self.ruby_system
dma_ports = board.get_dma_ports()
self._dma_controllers = []
for i, port in enumerate(dma_ports):
ctrl = DMAController(self.ruby_system.network, cache_line_size)
ctrl.dma_sequencer = DMASequencer(version=i, in_ports=port)
self._dma_controllers.append(ctrl)
ctrl.ruby_system = self.ruby_system
if board.has_dma_ports():
dma_ports = board.get_dma_ports()
for i, port in enumerate(dma_ports):
ctrl = DMAController(self.ruby_system.network, cache_line_size)
ctrl.dma_sequencer = DMASequencer(version=i, in_ports=port)
self._dma_controllers.append(ctrl)
ctrl.ruby_system = self.ruby_system
self.ruby_system.num_of_sequencers = len(self._l1_controllers) + len(
self._dma_controllers