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python: Add connect_interrupt() to mesi_two_level for non-X86

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The MESITwoLevelCacheHierarchy did not call `connect_interrupt()` on
CPUs if not ISA.X86. This patch fixes this.

Change-Id: I46ae19f588e2eadce60f145067e8a7cef0d44afd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49928
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
This commit is contained in:
Bobby R. Bruce
2021-09-03 12:21:11 -07:00
parent 7b84d5f946
commit 752394b243
1 changed files with 2 additions and 0 deletions
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src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
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@@ -140,6 +140,8 @@ class MESITwoLevelCacheHierarchy(
int_req_port = cache.sequencer.interrupt_out_port
int_resp_port = cache.sequencer.in_ports
core.connect_interrupt(int_req_port, int_resp_port)
else:
core.connect_interrupt()
self._l1_controllers.append(cache)