From 752394b243eda3773ea8421acc3758aaac0b60f0 Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Fri, 3 Sep 2021 12:21:11 -0700 Subject: [PATCH] python: Add connect_interrupt() to mesi_two_level for non-X86 The MESITwoLevelCacheHierarchy did not call `connect_interrupt()` on CPUs if not ISA.X86. This patch fixes this. Change-Id: I46ae19f588e2eadce60f145067e8a7cef0d44afd Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49928 Tested-by: kokoro Reviewed-by: Bobby R. Bruce Maintainer: Bobby R. Bruce --- .../cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py index d8c972ed06..64eabcd830 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py @@ -140,6 +140,8 @@ class MESITwoLevelCacheHierarchy( int_req_port = cache.sequencer.interrupt_out_port int_resp_port = cache.sequencer.in_ports core.connect_interrupt(int_req_port, int_resp_port) + else: + core.connect_interrupt() self._l1_controllers.append(cache)