diff --git a/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
index 64eabcd830..e5d0353a9a 100644
--- a/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
+++ b/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
@@ -169,13 +169,14 @@ class MESITwoLevelCacheHierarchy(
         for dir in self._directory_controllers:
             dir.ruby_system = self.ruby_system
 
-        dma_ports = board.get_dma_ports()
         self._dma_controllers = []
-        for i, port in enumerate(dma_ports):
-            ctrl = DMAController(self.ruby_system.network, cache_line_size)
-            ctrl.dma_sequencer = DMASequencer(version=i, in_ports=port)
-            self._dma_controllers.append(ctrl)
-            ctrl.ruby_system = self.ruby_system
+        if board.has_dma_ports():
+            dma_ports = board.get_dma_ports()
+            for i, port in enumerate(dma_ports):
+                ctrl = DMAController(self.ruby_system.network, cache_line_size)
+                ctrl.dma_sequencer = DMASequencer(version=i, in_ports=port)
+                self._dma_controllers.append(ctrl)
+                ctrl.ruby_system = self.ruby_system
 
         self.ruby_system.num_of_sequencers = len(self._l1_controllers) + len(
             self._dma_controllers