From 958029328f0b9c025fc00fa7062d8b238d141e5e Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Fri, 3 Sep 2021 12:23:29 -0700 Subject: [PATCH] python: Add `has_dma_ports` check to mesi_two_level Previously the MesiTwoLevelCacheHierarchy assumed the board had dma ports. This change adds a simple check and skips adding the DMASequencers if the board does not have any. Change-Id: I64ee68267d16c9d9a6096ba7fd660f04515b2b3c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49929 Tested-by: kokoro Reviewed-by: Bobby R. Bruce Maintainer: Bobby R. Bruce --- .../ruby/mesi_two_level_cache_hierarchy.py | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py index 64eabcd830..e5d0353a9a 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py @@ -169,13 +169,14 @@ class MESITwoLevelCacheHierarchy( for dir in self._directory_controllers: dir.ruby_system = self.ruby_system - dma_ports = board.get_dma_ports() self._dma_controllers = [] - for i, port in enumerate(dma_ports): - ctrl = DMAController(self.ruby_system.network, cache_line_size) - ctrl.dma_sequencer = DMASequencer(version=i, in_ports=port) - self._dma_controllers.append(ctrl) - ctrl.ruby_system = self.ruby_system + if board.has_dma_ports(): + dma_ports = board.get_dma_ports() + for i, port in enumerate(dma_ports): + ctrl = DMAController(self.ruby_system.network, cache_line_size) + ctrl.dma_sequencer = DMASequencer(version=i, in_ports=port) + self._dma_controllers.append(ctrl) + ctrl.ruby_system = self.ruby_system self.ruby_system.num_of_sequencers = len(self._l1_controllers) + len( self._dma_controllers