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cpu: Remove "lane" accessors from the ExecContext classes.

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These are not used by instructions. If something other than instructions
needs that style of access, it would use the ThreadContext, not the
ExecContext.

Change-Id: Ic74dcfd34f8bb0786bd2688b44d0d90714503637
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41897
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-02-25 00:28:54 -08:00
parent 25ecaaadbe
commit 69a66fc844
5 changed files with 0 additions and 316 deletions
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73
src/cpu/checker/cpu.hh
View File

@@ -218,79 +218,6 @@ class CheckerCPU : public BaseCPU, public ExecContext
return thread->getWritableVecReg(reg);
}
/** Vector Register Lane Interfaces. */
/** @{ */
/** Reads source vector 8bit operand. */
virtual ConstVecLane8
readVec8BitLaneOperand(const StaticInst *si, int idx) const override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecReg());
return thread->readVec8BitLaneReg(reg);
}
/** Reads source vector 16bit operand. */
virtual ConstVecLane16
readVec16BitLaneOperand(const StaticInst *si, int idx) const override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecReg());
return thread->readVec16BitLaneReg(reg);
}
/** Reads source vector 32bit operand. */
virtual ConstVecLane32
readVec32BitLaneOperand(const StaticInst *si, int idx) const override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecReg());
return thread->readVec32BitLaneReg(reg);
}
/** Reads source vector 64bit operand. */
virtual ConstVecLane64
readVec64BitLaneOperand(const StaticInst *si, int idx) const override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecReg());
return thread->readVec64BitLaneReg(reg);
}
/** Write a lane of the destination vector operand. */
template <typename LD>
void
setVecLaneOperandT(const StaticInst *si, int idx, const LD& val)
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecReg());
return thread->setVecLane(reg, val);
}
virtual void
setVecLaneOperand(const StaticInst *si, int idx,
const LaneData<LaneSize::Byte>& val) override
{
setVecLaneOperandT(si, idx, val);
}
virtual void
setVecLaneOperand(const StaticInst *si, int idx,
const LaneData<LaneSize::TwoByte>& val) override
{
setVecLaneOperandT(si, idx, val);
}
virtual void
setVecLaneOperand(const StaticInst *si, int idx,
const LaneData<LaneSize::FourByte>& val) override
{
setVecLaneOperandT(si, idx, val);
}
virtual void
setVecLaneOperand(const StaticInst *si, int idx,
const LaneData<LaneSize::EightByte>& val) override
{
setVecLaneOperandT(si, idx, val);
}
/** @} */
TheISA::VecElem
readVecElemOperand(const StaticInst *si, int idx) const override
{

30
src/cpu/exec_context.hh
View File

@@ -117,36 +117,6 @@ class ExecContext
const TheISA::VecRegContainer& val) = 0;
/** @} */
/** Vector Register Lane Interfaces. */
/** @{ */
/** Reads source vector 8bit operand. */
virtual ConstVecLane8 readVec8BitLaneOperand(
const StaticInst *si, int idx) const = 0;
/** Reads source vector 16bit operand. */
virtual ConstVecLane16 readVec16BitLaneOperand(
const StaticInst *si, int idx) const = 0;
/** Reads source vector 32bit operand. */
virtual ConstVecLane32 readVec32BitLaneOperand(
const StaticInst *si, int idx) const = 0;
/** Reads source vector 64bit operand. */
virtual ConstVecLane64 readVec64BitLaneOperand(
const StaticInst *si, int idx) const = 0;
/** Write a lane of the destination vector operand. */
/** @{ */
virtual void setVecLaneOperand(const StaticInst *si, int idx,
const LaneData<LaneSize::Byte>& val) = 0;
virtual void setVecLaneOperand(const StaticInst *si, int idx,
const LaneData<LaneSize::TwoByte>& val) = 0;
virtual void setVecLaneOperand(const StaticInst *si, int idx,
const LaneData<LaneSize::FourByte>& val) = 0;
virtual void setVecLaneOperand(const StaticInst *si, int idx,
const LaneData<LaneSize::EightByte>& val) = 0;
/** @} */
/** Vector Elem Interfaces. */
/** @{ */
/** Reads an element of a vector register. */

77
src/cpu/minor/exec_context.hh
View File

@@ -230,83 +230,6 @@ class ExecContext : public ::ExecContext
thread.setVecPredReg(reg, val);
}
/** Vector Register Lane Interfaces. */
/** @{ */
/** Reads source vector 8bit operand. */
ConstVecLane8
readVec8BitLaneOperand(const StaticInst *si, int idx) const
override
{
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isVecReg());
return thread.readVec8BitLaneReg(reg);
}
/** Reads source vector 16bit operand. */
ConstVecLane16
readVec16BitLaneOperand(const StaticInst *si, int idx) const
override
{
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isVecReg());
return thread.readVec16BitLaneReg(reg);
}
/** Reads source vector 32bit operand. */
ConstVecLane32
readVec32BitLaneOperand(const StaticInst *si, int idx) const
override
{
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isVecReg());
return thread.readVec32BitLaneReg(reg);
}
/** Reads source vector 64bit operand. */
ConstVecLane64
readVec64BitLaneOperand(const StaticInst *si, int idx) const
override
{
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isVecReg());
return thread.readVec64BitLaneReg(reg);
}
/** Write a lane of the destination vector operand. */
template <typename LD>
void
setVecLaneOperandT(const StaticInst *si, int idx, const LD& val)
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecReg());
return thread.setVecLane(reg, val);
}
virtual void
setVecLaneOperand(const StaticInst *si, int idx,
const LaneData<LaneSize::Byte>& val) override
{
setVecLaneOperandT(si, idx, val);
}
virtual void
setVecLaneOperand(const StaticInst *si, int idx,
const LaneData<LaneSize::TwoByte>& val) override
{
setVecLaneOperandT(si, idx, val);
}
virtual void
setVecLaneOperand(const StaticInst *si, int idx,
const LaneData<LaneSize::FourByte>& val) override
{
setVecLaneOperandT(si, idx, val);
}
virtual void
setVecLaneOperand(const StaticInst *si, int idx,
const LaneData<LaneSize::EightByte>& val) override
{
setVecLaneOperandT(si, idx, val);
}
/** @} */
void
setVecElemOperand(const StaticInst *si, int idx,
const TheISA::VecElem val) override

67
src/cpu/o3/dyn_inst.hh
View File

@@ -268,73 +268,6 @@ class BaseO3DynInst : public BaseDynInst<Impl>
return this->cpu->getWritableVecReg(this->regs.renamedDestIdx(idx));
}
/** Vector Register Lane Interfaces. */
/** @{ */
/** Reads source vector 8bit operand. */
ConstVecLane8
readVec8BitLaneOperand(const StaticInst *si, int idx) const override
{
return cpu->template readVecLane<uint8_t>(
this->regs.renamedSrcIdx(idx));
}
/** Reads source vector 16bit operand. */
ConstVecLane16
readVec16BitLaneOperand(const StaticInst *si, int idx) const override
{
return cpu->template readVecLane<uint16_t>(
this->regs.renamedSrcIdx(idx));
}
/** Reads source vector 32bit operand. */
ConstVecLane32
readVec32BitLaneOperand(const StaticInst *si, int idx) const override
{
return cpu->template readVecLane<uint32_t>(
this->regs.renamedSrcIdx(idx));
}
/** Reads source vector 64bit operand. */
ConstVecLane64
readVec64BitLaneOperand(const StaticInst *si, int idx) const override
{
return cpu->template readVecLane<uint64_t>(
this->regs.renamedSrcIdx(idx));
}
/** Write a lane of the destination vector operand. */
template <typename LD>
void
setVecLaneOperandT(const StaticInst *si, int idx, const LD& val)
{
return cpu->template setVecLane(this->regs.renamedDestIdx(idx), val);
}
void
setVecLaneOperand(const StaticInst *si, int idx,
const LaneData<LaneSize::Byte>& val) override
{
return setVecLaneOperandT(si, idx, val);
}
void
setVecLaneOperand(const StaticInst *si, int idx,
const LaneData<LaneSize::TwoByte>& val) override
{
return setVecLaneOperandT(si, idx, val);
}
void
setVecLaneOperand(const StaticInst *si, int idx,
const LaneData<LaneSize::FourByte>& val) override
{
return setVecLaneOperandT(si, idx, val);
}
void
setVecLaneOperand(const StaticInst *si, int idx,
const LaneData<LaneSize::EightByte>& val) override
{
return setVecLaneOperandT(si, idx, val);
}
/** @} */
TheISA::VecElem
readVecElemOperand(const StaticInst *si, int idx) const override
{

69
src/cpu/simple/exec_context.hh
View File

@@ -344,75 +344,6 @@ class SimpleExecContext : public ExecContext
thread->setVecReg(reg, val);
}
/** Vector Register Lane Interfaces. */
/** @{ */
/** Reads source vector lane. */
template <typename VE>
VecLaneT<VE, true>
readVecLaneOperand(const StaticInst *si, int idx) const
{
execContextStats.numVecRegReads++;
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isVecReg());
return thread->readVecLane<VE>(reg);
}
/** Reads source vector 8bit operand. */
virtual ConstVecLane8
readVec8BitLaneOperand(const StaticInst *si, int idx) const
override
{ return readVecLaneOperand<uint8_t>(si, idx); }
/** Reads source vector 16bit operand. */
virtual ConstVecLane16
readVec16BitLaneOperand(const StaticInst *si, int idx) const
override
{ return readVecLaneOperand<uint16_t>(si, idx); }
/** Reads source vector 32bit operand. */
virtual ConstVecLane32
readVec32BitLaneOperand(const StaticInst *si, int idx) const
override
{ return readVecLaneOperand<uint32_t>(si, idx); }
/** Reads source vector 64bit operand. */
virtual ConstVecLane64
readVec64BitLaneOperand(const StaticInst *si, int idx) const
override
{ return readVecLaneOperand<uint64_t>(si, idx); }
/** Write a lane of the destination vector operand. */
template <typename LD>
void
setVecLaneOperandT(const StaticInst *si, int idx,
const LD& val)
{
execContextStats.numVecRegWrites++;
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecReg());
return thread->setVecLane(reg, val);
}
/** Write a lane of the destination vector operand. */
virtual void
setVecLaneOperand(const StaticInst *si, int idx,
const LaneData<LaneSize::Byte>& val) override
{ return setVecLaneOperandT(si, idx, val); }
/** Write a lane of the destination vector operand. */
virtual void
setVecLaneOperand(const StaticInst *si, int idx,
const LaneData<LaneSize::TwoByte>& val) override
{ return setVecLaneOperandT(si, idx, val); }
/** Write a lane of the destination vector operand. */
virtual void
setVecLaneOperand(const StaticInst *si, int idx,
const LaneData<LaneSize::FourByte>& val) override
{ return setVecLaneOperandT(si, idx, val); }
/** Write a lane of the destination vector operand. */
virtual void
setVecLaneOperand(const StaticInst *si, int idx,
const LaneData<LaneSize::EightByte>& val) override
{ return setVecLaneOperandT(si, idx, val); }
/** @} */
/** Reads an element of a vector register. */
TheISA::VecElem
readVecElemOperand(const StaticInst *si, int idx) const override