diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 42a38fc2e2..0900125668 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -218,79 +218,6 @@ class CheckerCPU : public BaseCPU, public ExecContext
         return thread->getWritableVecReg(reg);
     }
 
-    /** Vector Register Lane Interfaces. */
-    /** @{ */
-    /** Reads source vector 8bit operand. */
-    virtual ConstVecLane8
-    readVec8BitLaneOperand(const StaticInst *si, int idx) const override
-    {
-        const RegId& reg = si->destRegIdx(idx);
-        assert(reg.isVecReg());
-        return thread->readVec8BitLaneReg(reg);
-    }
-
-    /** Reads source vector 16bit operand. */
-    virtual ConstVecLane16
-    readVec16BitLaneOperand(const StaticInst *si, int idx) const override
-    {
-        const RegId& reg = si->destRegIdx(idx);
-        assert(reg.isVecReg());
-        return thread->readVec16BitLaneReg(reg);
-    }
-
-    /** Reads source vector 32bit operand. */
-    virtual ConstVecLane32
-    readVec32BitLaneOperand(const StaticInst *si, int idx) const override
-    {
-        const RegId& reg = si->destRegIdx(idx);
-        assert(reg.isVecReg());
-        return thread->readVec32BitLaneReg(reg);
-    }
-
-    /** Reads source vector 64bit operand. */
-    virtual ConstVecLane64
-    readVec64BitLaneOperand(const StaticInst *si, int idx) const override
-    {
-        const RegId& reg = si->destRegIdx(idx);
-        assert(reg.isVecReg());
-        return thread->readVec64BitLaneReg(reg);
-    }
-
-    /** Write a lane of the destination vector operand. */
-    template <typename LD>
-    void
-    setVecLaneOperandT(const StaticInst *si, int idx, const LD& val)
-    {
-        const RegId& reg = si->destRegIdx(idx);
-        assert(reg.isVecReg());
-        return thread->setVecLane(reg, val);
-    }
-    virtual void
-    setVecLaneOperand(const StaticInst *si, int idx,
-            const LaneData<LaneSize::Byte>& val) override
-    {
-        setVecLaneOperandT(si, idx, val);
-    }
-    virtual void
-    setVecLaneOperand(const StaticInst *si, int idx,
-            const LaneData<LaneSize::TwoByte>& val) override
-    {
-        setVecLaneOperandT(si, idx, val);
-    }
-    virtual void
-    setVecLaneOperand(const StaticInst *si, int idx,
-            const LaneData<LaneSize::FourByte>& val) override
-    {
-        setVecLaneOperandT(si, idx, val);
-    }
-    virtual void
-    setVecLaneOperand(const StaticInst *si, int idx,
-            const LaneData<LaneSize::EightByte>& val) override
-    {
-        setVecLaneOperandT(si, idx, val);
-    }
-    /** @} */
-
     TheISA::VecElem
     readVecElemOperand(const StaticInst *si, int idx) const override
     {
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index 42dafbcacd..3c40f31621 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -117,36 +117,6 @@ class ExecContext
             const TheISA::VecRegContainer& val) = 0;
     /** @} */
 
-    /** Vector Register Lane Interfaces. */
-    /** @{ */
-    /** Reads source vector 8bit operand. */
-    virtual ConstVecLane8 readVec8BitLaneOperand(
-            const StaticInst *si, int idx) const = 0;
-
-    /** Reads source vector 16bit operand. */
-    virtual ConstVecLane16 readVec16BitLaneOperand(
-            const StaticInst *si, int idx) const = 0;
-
-    /** Reads source vector 32bit operand. */
-    virtual ConstVecLane32 readVec32BitLaneOperand(
-            const StaticInst *si, int idx) const = 0;
-
-    /** Reads source vector 64bit operand. */
-    virtual ConstVecLane64 readVec64BitLaneOperand(
-            const StaticInst *si, int idx) const = 0;
-
-    /** Write a lane of the destination vector operand. */
-    /** @{ */
-    virtual void setVecLaneOperand(const StaticInst *si, int idx,
-            const LaneData<LaneSize::Byte>& val) = 0;
-    virtual void setVecLaneOperand(const StaticInst *si, int idx,
-            const LaneData<LaneSize::TwoByte>& val) = 0;
-    virtual void setVecLaneOperand(const StaticInst *si, int idx,
-            const LaneData<LaneSize::FourByte>& val) = 0;
-    virtual void setVecLaneOperand(const StaticInst *si, int idx,
-            const LaneData<LaneSize::EightByte>& val) = 0;
-    /** @} */
-
     /** Vector Elem Interfaces. */
     /** @{ */
     /** Reads an element of a vector register. */
diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 153fe29104..58f4b4b987 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -230,83 +230,6 @@ class ExecContext : public ::ExecContext
         thread.setVecPredReg(reg, val);
     }
 
-    /** Vector Register Lane Interfaces. */
-    /** @{ */
-    /** Reads source vector 8bit operand. */
-    ConstVecLane8
-    readVec8BitLaneOperand(const StaticInst *si, int idx) const
-                            override
-    {
-        const RegId& reg = si->srcRegIdx(idx);
-        assert(reg.isVecReg());
-        return thread.readVec8BitLaneReg(reg);
-    }
-
-    /** Reads source vector 16bit operand. */
-    ConstVecLane16
-    readVec16BitLaneOperand(const StaticInst *si, int idx) const
-                            override
-    {
-        const RegId& reg = si->srcRegIdx(idx);
-        assert(reg.isVecReg());
-        return thread.readVec16BitLaneReg(reg);
-    }
-
-    /** Reads source vector 32bit operand. */
-    ConstVecLane32
-    readVec32BitLaneOperand(const StaticInst *si, int idx) const
-                            override
-    {
-        const RegId& reg = si->srcRegIdx(idx);
-        assert(reg.isVecReg());
-        return thread.readVec32BitLaneReg(reg);
-    }
-
-    /** Reads source vector 64bit operand. */
-    ConstVecLane64
-    readVec64BitLaneOperand(const StaticInst *si, int idx) const
-                            override
-    {
-        const RegId& reg = si->srcRegIdx(idx);
-        assert(reg.isVecReg());
-        return thread.readVec64BitLaneReg(reg);
-    }
-
-    /** Write a lane of the destination vector operand. */
-    template <typename LD>
-    void
-    setVecLaneOperandT(const StaticInst *si, int idx, const LD& val)
-    {
-        const RegId& reg = si->destRegIdx(idx);
-        assert(reg.isVecReg());
-        return thread.setVecLane(reg, val);
-    }
-    virtual void
-    setVecLaneOperand(const StaticInst *si, int idx,
-            const LaneData<LaneSize::Byte>& val) override
-    {
-        setVecLaneOperandT(si, idx, val);
-    }
-    virtual void
-    setVecLaneOperand(const StaticInst *si, int idx,
-            const LaneData<LaneSize::TwoByte>& val) override
-    {
-        setVecLaneOperandT(si, idx, val);
-    }
-    virtual void
-    setVecLaneOperand(const StaticInst *si, int idx,
-            const LaneData<LaneSize::FourByte>& val) override
-    {
-        setVecLaneOperandT(si, idx, val);
-    }
-    virtual void
-    setVecLaneOperand(const StaticInst *si, int idx,
-            const LaneData<LaneSize::EightByte>& val) override
-    {
-        setVecLaneOperandT(si, idx, val);
-    }
-    /** @} */
-
     void
     setVecElemOperand(const StaticInst *si, int idx,
                       const TheISA::VecElem val) override
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 7a54c7fd9b..80eb655566 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -268,73 +268,6 @@ class BaseO3DynInst : public BaseDynInst<Impl>
         return this->cpu->getWritableVecReg(this->regs.renamedDestIdx(idx));
     }
 
-    /** Vector Register Lane Interfaces. */
-    /** @{ */
-    /** Reads source vector 8bit operand. */
-    ConstVecLane8
-    readVec8BitLaneOperand(const StaticInst *si, int idx) const override
-    {
-        return cpu->template readVecLane<uint8_t>(
-                this->regs.renamedSrcIdx(idx));
-    }
-
-    /** Reads source vector 16bit operand. */
-    ConstVecLane16
-    readVec16BitLaneOperand(const StaticInst *si, int idx) const override
-    {
-        return cpu->template readVecLane<uint16_t>(
-                this->regs.renamedSrcIdx(idx));
-    }
-
-    /** Reads source vector 32bit operand. */
-    ConstVecLane32
-    readVec32BitLaneOperand(const StaticInst *si, int idx) const override
-    {
-        return cpu->template readVecLane<uint32_t>(
-                this->regs.renamedSrcIdx(idx));
-    }
-
-    /** Reads source vector 64bit operand. */
-    ConstVecLane64
-    readVec64BitLaneOperand(const StaticInst *si, int idx) const override
-    {
-        return cpu->template readVecLane<uint64_t>(
-                this->regs.renamedSrcIdx(idx));
-    }
-
-    /** Write a lane of the destination vector operand. */
-    template <typename LD>
-    void
-    setVecLaneOperandT(const StaticInst *si, int idx, const LD& val)
-    {
-        return cpu->template setVecLane(this->regs.renamedDestIdx(idx), val);
-    }
-    void
-    setVecLaneOperand(const StaticInst *si, int idx,
-            const LaneData<LaneSize::Byte>& val) override
-    {
-        return setVecLaneOperandT(si, idx, val);
-    }
-    void
-    setVecLaneOperand(const StaticInst *si, int idx,
-            const LaneData<LaneSize::TwoByte>& val) override
-    {
-        return setVecLaneOperandT(si, idx, val);
-    }
-    void
-    setVecLaneOperand(const StaticInst *si, int idx,
-            const LaneData<LaneSize::FourByte>& val) override
-    {
-        return setVecLaneOperandT(si, idx, val);
-    }
-    void
-    setVecLaneOperand(const StaticInst *si, int idx,
-            const LaneData<LaneSize::EightByte>& val) override
-    {
-        return setVecLaneOperandT(si, idx, val);
-    }
-    /** @} */
-
     TheISA::VecElem
     readVecElemOperand(const StaticInst *si, int idx) const override
     {
diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index 235c703f05..218f3504e3 100644
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -344,75 +344,6 @@ class SimpleExecContext : public ExecContext
         thread->setVecReg(reg, val);
     }
 
-    /** Vector Register Lane Interfaces. */
-    /** @{ */
-    /** Reads source vector lane. */
-    template <typename VE>
-    VecLaneT<VE, true>
-    readVecLaneOperand(const StaticInst *si, int idx) const
-    {
-        execContextStats.numVecRegReads++;
-        const RegId& reg = si->srcRegIdx(idx);
-        assert(reg.isVecReg());
-        return thread->readVecLane<VE>(reg);
-    }
-    /** Reads source vector 8bit operand. */
-    virtual ConstVecLane8
-    readVec8BitLaneOperand(const StaticInst *si, int idx) const
-                            override
-    { return readVecLaneOperand<uint8_t>(si, idx); }
-
-    /** Reads source vector 16bit operand. */
-    virtual ConstVecLane16
-    readVec16BitLaneOperand(const StaticInst *si, int idx) const
-                            override
-    { return readVecLaneOperand<uint16_t>(si, idx); }
-
-    /** Reads source vector 32bit operand. */
-    virtual ConstVecLane32
-    readVec32BitLaneOperand(const StaticInst *si, int idx) const
-                            override
-    { return readVecLaneOperand<uint32_t>(si, idx); }
-
-    /** Reads source vector 64bit operand. */
-    virtual ConstVecLane64
-    readVec64BitLaneOperand(const StaticInst *si, int idx) const
-                            override
-    { return readVecLaneOperand<uint64_t>(si, idx); }
-
-    /** Write a lane of the destination vector operand. */
-    template <typename LD>
-    void
-    setVecLaneOperandT(const StaticInst *si, int idx,
-            const LD& val)
-    {
-        execContextStats.numVecRegWrites++;
-        const RegId& reg = si->destRegIdx(idx);
-        assert(reg.isVecReg());
-        return thread->setVecLane(reg, val);
-    }
-    /** Write a lane of the destination vector operand. */
-    virtual void
-    setVecLaneOperand(const StaticInst *si, int idx,
-            const LaneData<LaneSize::Byte>& val) override
-    { return setVecLaneOperandT(si, idx, val); }
-    /** Write a lane of the destination vector operand. */
-    virtual void
-    setVecLaneOperand(const StaticInst *si, int idx,
-            const LaneData<LaneSize::TwoByte>& val) override
-    { return setVecLaneOperandT(si, idx, val); }
-    /** Write a lane of the destination vector operand. */
-    virtual void
-    setVecLaneOperand(const StaticInst *si, int idx,
-            const LaneData<LaneSize::FourByte>& val) override
-    { return setVecLaneOperandT(si, idx, val); }
-    /** Write a lane of the destination vector operand. */
-    virtual void
-    setVecLaneOperand(const StaticInst *si, int idx,
-            const LaneData<LaneSize::EightByte>& val) override
-    { return setVecLaneOperandT(si, idx, val); }
-    /** @} */
-
     /** Reads an element of a vector register. */
     TheISA::VecElem
     readVecElemOperand(const StaticInst *si, int idx) const override