From 69a66fc844c0519f14232f97901a5869ec5e484e Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Thu, 25 Feb 2021 00:28:54 -0800 Subject: [PATCH] cpu: Remove "lane" accessors from the ExecContext classes. These are not used by instructions. If something other than instructions needs that style of access, it would use the ThreadContext, not the ExecContext. Change-Id: Ic74dcfd34f8bb0786bd2688b44d0d90714503637 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41897 Reviewed-by: Gabe Black Maintainer: Gabe Black Tested-by: kokoro --- src/cpu/checker/cpu.hh | 73 -------------------------------- src/cpu/exec_context.hh | 30 ------------- src/cpu/minor/exec_context.hh | 77 ---------------------------------- src/cpu/o3/dyn_inst.hh | 67 ----------------------------- src/cpu/simple/exec_context.hh | 69 ------------------------------ 5 files changed, 316 deletions(-) diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 42a38fc2e2..0900125668 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -218,79 +218,6 @@ class CheckerCPU : public BaseCPU, public ExecContext return thread->getWritableVecReg(reg); } - /** Vector Register Lane Interfaces. */ - /** @{ */ - /** Reads source vector 8bit operand. */ - virtual ConstVecLane8 - readVec8BitLaneOperand(const StaticInst *si, int idx) const override - { - const RegId& reg = si->destRegIdx(idx); - assert(reg.isVecReg()); - return thread->readVec8BitLaneReg(reg); - } - - /** Reads source vector 16bit operand. */ - virtual ConstVecLane16 - readVec16BitLaneOperand(const StaticInst *si, int idx) const override - { - const RegId& reg = si->destRegIdx(idx); - assert(reg.isVecReg()); - return thread->readVec16BitLaneReg(reg); - } - - /** Reads source vector 32bit operand. */ - virtual ConstVecLane32 - readVec32BitLaneOperand(const StaticInst *si, int idx) const override - { - const RegId& reg = si->destRegIdx(idx); - assert(reg.isVecReg()); - return thread->readVec32BitLaneReg(reg); - } - - /** Reads source vector 64bit operand. */ - virtual ConstVecLane64 - readVec64BitLaneOperand(const StaticInst *si, int idx) const override - { - const RegId& reg = si->destRegIdx(idx); - assert(reg.isVecReg()); - return thread->readVec64BitLaneReg(reg); - } - - /** Write a lane of the destination vector operand. */ - template - void - setVecLaneOperandT(const StaticInst *si, int idx, const LD& val) - { - const RegId& reg = si->destRegIdx(idx); - assert(reg.isVecReg()); - return thread->setVecLane(reg, val); - } - virtual void - setVecLaneOperand(const StaticInst *si, int idx, - const LaneData& val) override - { - setVecLaneOperandT(si, idx, val); - } - virtual void - setVecLaneOperand(const StaticInst *si, int idx, - const LaneData& val) override - { - setVecLaneOperandT(si, idx, val); - } - virtual void - setVecLaneOperand(const StaticInst *si, int idx, - const LaneData& val) override - { - setVecLaneOperandT(si, idx, val); - } - virtual void - setVecLaneOperand(const StaticInst *si, int idx, - const LaneData& val) override - { - setVecLaneOperandT(si, idx, val); - } - /** @} */ - TheISA::VecElem readVecElemOperand(const StaticInst *si, int idx) const override { diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh index 42dafbcacd..3c40f31621 100644 --- a/src/cpu/exec_context.hh +++ b/src/cpu/exec_context.hh @@ -117,36 +117,6 @@ class ExecContext const TheISA::VecRegContainer& val) = 0; /** @} */ - /** Vector Register Lane Interfaces. */ - /** @{ */ - /** Reads source vector 8bit operand. */ - virtual ConstVecLane8 readVec8BitLaneOperand( - const StaticInst *si, int idx) const = 0; - - /** Reads source vector 16bit operand. */ - virtual ConstVecLane16 readVec16BitLaneOperand( - const StaticInst *si, int idx) const = 0; - - /** Reads source vector 32bit operand. */ - virtual ConstVecLane32 readVec32BitLaneOperand( - const StaticInst *si, int idx) const = 0; - - /** Reads source vector 64bit operand. */ - virtual ConstVecLane64 readVec64BitLaneOperand( - const StaticInst *si, int idx) const = 0; - - /** Write a lane of the destination vector operand. */ - /** @{ */ - virtual void setVecLaneOperand(const StaticInst *si, int idx, - const LaneData& val) = 0; - virtual void setVecLaneOperand(const StaticInst *si, int idx, - const LaneData& val) = 0; - virtual void setVecLaneOperand(const StaticInst *si, int idx, - const LaneData& val) = 0; - virtual void setVecLaneOperand(const StaticInst *si, int idx, - const LaneData& val) = 0; - /** @} */ - /** Vector Elem Interfaces. */ /** @{ */ /** Reads an element of a vector register. */ diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh index 153fe29104..58f4b4b987 100644 --- a/src/cpu/minor/exec_context.hh +++ b/src/cpu/minor/exec_context.hh @@ -230,83 +230,6 @@ class ExecContext : public ::ExecContext thread.setVecPredReg(reg, val); } - /** Vector Register Lane Interfaces. */ - /** @{ */ - /** Reads source vector 8bit operand. */ - ConstVecLane8 - readVec8BitLaneOperand(const StaticInst *si, int idx) const - override - { - const RegId& reg = si->srcRegIdx(idx); - assert(reg.isVecReg()); - return thread.readVec8BitLaneReg(reg); - } - - /** Reads source vector 16bit operand. */ - ConstVecLane16 - readVec16BitLaneOperand(const StaticInst *si, int idx) const - override - { - const RegId& reg = si->srcRegIdx(idx); - assert(reg.isVecReg()); - return thread.readVec16BitLaneReg(reg); - } - - /** Reads source vector 32bit operand. */ - ConstVecLane32 - readVec32BitLaneOperand(const StaticInst *si, int idx) const - override - { - const RegId& reg = si->srcRegIdx(idx); - assert(reg.isVecReg()); - return thread.readVec32BitLaneReg(reg); - } - - /** Reads source vector 64bit operand. */ - ConstVecLane64 - readVec64BitLaneOperand(const StaticInst *si, int idx) const - override - { - const RegId& reg = si->srcRegIdx(idx); - assert(reg.isVecReg()); - return thread.readVec64BitLaneReg(reg); - } - - /** Write a lane of the destination vector operand. */ - template - void - setVecLaneOperandT(const StaticInst *si, int idx, const LD& val) - { - const RegId& reg = si->destRegIdx(idx); - assert(reg.isVecReg()); - return thread.setVecLane(reg, val); - } - virtual void - setVecLaneOperand(const StaticInst *si, int idx, - const LaneData& val) override - { - setVecLaneOperandT(si, idx, val); - } - virtual void - setVecLaneOperand(const StaticInst *si, int idx, - const LaneData& val) override - { - setVecLaneOperandT(si, idx, val); - } - virtual void - setVecLaneOperand(const StaticInst *si, int idx, - const LaneData& val) override - { - setVecLaneOperandT(si, idx, val); - } - virtual void - setVecLaneOperand(const StaticInst *si, int idx, - const LaneData& val) override - { - setVecLaneOperandT(si, idx, val); - } - /** @} */ - void setVecElemOperand(const StaticInst *si, int idx, const TheISA::VecElem val) override diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh index 7a54c7fd9b..80eb655566 100644 --- a/src/cpu/o3/dyn_inst.hh +++ b/src/cpu/o3/dyn_inst.hh @@ -268,73 +268,6 @@ class BaseO3DynInst : public BaseDynInst return this->cpu->getWritableVecReg(this->regs.renamedDestIdx(idx)); } - /** Vector Register Lane Interfaces. */ - /** @{ */ - /** Reads source vector 8bit operand. */ - ConstVecLane8 - readVec8BitLaneOperand(const StaticInst *si, int idx) const override - { - return cpu->template readVecLane( - this->regs.renamedSrcIdx(idx)); - } - - /** Reads source vector 16bit operand. */ - ConstVecLane16 - readVec16BitLaneOperand(const StaticInst *si, int idx) const override - { - return cpu->template readVecLane( - this->regs.renamedSrcIdx(idx)); - } - - /** Reads source vector 32bit operand. */ - ConstVecLane32 - readVec32BitLaneOperand(const StaticInst *si, int idx) const override - { - return cpu->template readVecLane( - this->regs.renamedSrcIdx(idx)); - } - - /** Reads source vector 64bit operand. */ - ConstVecLane64 - readVec64BitLaneOperand(const StaticInst *si, int idx) const override - { - return cpu->template readVecLane( - this->regs.renamedSrcIdx(idx)); - } - - /** Write a lane of the destination vector operand. */ - template - void - setVecLaneOperandT(const StaticInst *si, int idx, const LD& val) - { - return cpu->template setVecLane(this->regs.renamedDestIdx(idx), val); - } - void - setVecLaneOperand(const StaticInst *si, int idx, - const LaneData& val) override - { - return setVecLaneOperandT(si, idx, val); - } - void - setVecLaneOperand(const StaticInst *si, int idx, - const LaneData& val) override - { - return setVecLaneOperandT(si, idx, val); - } - void - setVecLaneOperand(const StaticInst *si, int idx, - const LaneData& val) override - { - return setVecLaneOperandT(si, idx, val); - } - void - setVecLaneOperand(const StaticInst *si, int idx, - const LaneData& val) override - { - return setVecLaneOperandT(si, idx, val); - } - /** @} */ - TheISA::VecElem readVecElemOperand(const StaticInst *si, int idx) const override { diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh index 235c703f05..218f3504e3 100644 --- a/src/cpu/simple/exec_context.hh +++ b/src/cpu/simple/exec_context.hh @@ -344,75 +344,6 @@ class SimpleExecContext : public ExecContext thread->setVecReg(reg, val); } - /** Vector Register Lane Interfaces. */ - /** @{ */ - /** Reads source vector lane. */ - template - VecLaneT - readVecLaneOperand(const StaticInst *si, int idx) const - { - execContextStats.numVecRegReads++; - const RegId& reg = si->srcRegIdx(idx); - assert(reg.isVecReg()); - return thread->readVecLane(reg); - } - /** Reads source vector 8bit operand. */ - virtual ConstVecLane8 - readVec8BitLaneOperand(const StaticInst *si, int idx) const - override - { return readVecLaneOperand(si, idx); } - - /** Reads source vector 16bit operand. */ - virtual ConstVecLane16 - readVec16BitLaneOperand(const StaticInst *si, int idx) const - override - { return readVecLaneOperand(si, idx); } - - /** Reads source vector 32bit operand. */ - virtual ConstVecLane32 - readVec32BitLaneOperand(const StaticInst *si, int idx) const - override - { return readVecLaneOperand(si, idx); } - - /** Reads source vector 64bit operand. */ - virtual ConstVecLane64 - readVec64BitLaneOperand(const StaticInst *si, int idx) const - override - { return readVecLaneOperand(si, idx); } - - /** Write a lane of the destination vector operand. */ - template - void - setVecLaneOperandT(const StaticInst *si, int idx, - const LD& val) - { - execContextStats.numVecRegWrites++; - const RegId& reg = si->destRegIdx(idx); - assert(reg.isVecReg()); - return thread->setVecLane(reg, val); - } - /** Write a lane of the destination vector operand. */ - virtual void - setVecLaneOperand(const StaticInst *si, int idx, - const LaneData& val) override - { return setVecLaneOperandT(si, idx, val); } - /** Write a lane of the destination vector operand. */ - virtual void - setVecLaneOperand(const StaticInst *si, int idx, - const LaneData& val) override - { return setVecLaneOperandT(si, idx, val); } - /** Write a lane of the destination vector operand. */ - virtual void - setVecLaneOperand(const StaticInst *si, int idx, - const LaneData& val) override - { return setVecLaneOperandT(si, idx, val); } - /** Write a lane of the destination vector operand. */ - virtual void - setVecLaneOperand(const StaticInst *si, int idx, - const LaneData& val) override - { return setVecLaneOperandT(si, idx, val); } - /** @} */ - /** Reads an element of a vector register. */ TheISA::VecElem readVecElemOperand(const StaticInst *si, int idx) const override